A pipelined microprocessor for logic programming languages

Hiroshi Nakashima; Yasutaka Takeda; Katsuto Nakajima; Hideki Andou; Kiyohiro Furutani

A pipelined microprocessor for logic programming languages

Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Hideki Andou, Kiyohiro Furutani

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.

Original language	English
Title of host publication	Proceedings - IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors
Publisher	Publ by IEEE
Pages	355-359
Number of pages	5
ISBN (Print)	O81862079X
Publication status	Published - Sep 1990
Externally published	Yes
Event	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA Duration: Sep 17 1990 → Sep 19 1990

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

Other	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
City	Cambridge, MA, USA
Period	9/17/90 → 9/19/90

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

A pipelined microprocessor for logic programming languages. / Nakashima, Hiroshi; Takeda, Yasutaka; Nakajima, Katsuto; Andou, Hideki; Furutani, Kiyohiro.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, 1990. p. 355-359 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nakashima, H, Takeda, Y, Nakajima, K, Andou, H & Furutani, K 1990, A pipelined microprocessor for logic programming languages. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, Publ by IEEE, pp. 355-359, Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90, Cambridge, MA, USA, 9/17/90.

Nakashima, Hiroshi ; Takeda, Yasutaka ; Nakajima, Katsuto ; Andou, Hideki ; Furutani, Kiyohiro. / A pipelined microprocessor for logic programming languages. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, 1990. pp. 355-359 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

@inproceedings{8b18c853f4004d9db88f8e6a5c3020ed,

title = "A pipelined microprocessor for logic programming languages",

abstract = "The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.",

author = "Hiroshi Nakashima and Yasutaka Takeda and Katsuto Nakajima and Hideki Andou and Kiyohiro Furutani",

note = "Copyright: Copyright 2004 Elsevier B.V., All rights reserved.; Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 ; Conference date: 17-09-1990 Through 19-09-1990",

year = "1990",

month = sep,

language = "English",

isbn = "O81862079X",

series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",

publisher = "Publ by IEEE",

pages = "355--359",

booktitle = "Proceedings - IEEE International Conference on Computer Design",

}

TY - GEN

T1 - A pipelined microprocessor for logic programming languages

AU - Nakashima, Hiroshi

AU - Takeda, Yasutaka

AU - Nakajima, Katsuto

AU - Andou, Hideki

AU - Furutani, Kiyohiro

PY - 1990/9

Y1 - 1990/9

N2 - The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.

AB - The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.

UR - http://www.scopus.com/inward/record.url?scp=0025486857&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025486857&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0025486857

SN - O81862079X

T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

SP - 355

EP - 359

BT - Proceedings - IEEE International Conference on Computer Design

PB - Publ by IEEE

T2 - Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90

Y2 - 17 September 1990 through 19 September 1990

ER -

A pipelined microprocessor for logic programming languages

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this