A pipelined microprocessor for logic programming languages

Hiroshi Nakashima; Yasutaka Takeda; Katsuto Nakajima; Hideki Andou; Kiyohiro Furutani

A pipelined microprocessor for logic programming languages

Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Hideki Andou, Kiyohiro Furutani

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.

Original language	English
Title of host publication	Proceedings - IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors
Publisher	Publ by IEEE
Pages	355-359
Number of pages	5
ISBN (Print)	O81862079X
Publication status	Published - Sep 1990
Externally published	Yes
Event	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA Duration: Sep 17 1990 → Sep 19 1990

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

Other	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
City	Cambridge, MA, USA
Period	9/17/90 → 9/19/90

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

A pipelined microprocessor for logic programming languages. / Nakashima, Hiroshi; Takeda, Yasutaka; Nakajima, Katsuto et al.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, 1990. p. 355-359 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nakashima, H, Takeda, Y, Nakajima, K, Andou, H & Furutani, K 1990, A pipelined microprocessor for logic programming languages. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, Publ by IEEE, pp. 355-359, Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90, Cambridge, MA, USA, 9/17/90.

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A pipelined microprocessor for logic programming languages

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All Science Journal Classification (ASJC) codes

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