TY - GEN
T1 - A pipelined microprocessor for logic programming languages
AU - Nakashima, Hiroshi
AU - Takeda, Yasutaka
AU - Nakajima, Katsuto
AU - Andou, Hideki
AU - Furutani, Kiyohiro
N1 - Copyright:
Copyright 2004 Elsevier B.V., All rights reserved.
PY - 1990/9
Y1 - 1990/9
N2 - The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.
AB - The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.
UR - http://www.scopus.com/inward/record.url?scp=0025486857&partnerID=8YFLogxK
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M3 - Conference contribution
AN - SCOPUS:0025486857
SN - O81862079X
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 355
EP - 359
BT - Proceedings - IEEE International Conference on Computer Design
PB - Publ by IEEE
T2 - Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
Y2 - 17 September 1990 through 19 September 1990
ER -