Abstract
For embedded systems, concurrency is required to respond to various changes in real world. Real-time processing is required also, because the response typically has a time limit. The concurrency is implemented by processing Tasks or Interrupt Service Routines (ISRs) concurrently. And the necessity of mutual exclusion arises in concurrent processing, to maintain integrity of shared data. Task execution is scheduled by Real-time OS (RTOS), and mutual exclusion is serviced by semaphore. However approximately 30% of embedded systems do not use RTOS. These systems have no notion of Tasks, and are purely driven by ISRs. As the sole mutual exclusion method between ISRs, a pair of interrupt disable/enable instructions provided by CPU is used in these systems. This method enables a lower priority ISR to protect its critical section from higher priority ISRs, but it also defers execution of unrelated ISRs as it disables all external interrupts. We have resolved this timing issue with an ISR-callable semaphore, but that design was not priority inversion safe. Namely a middle priority ISR may indirectly block a higher priority ISR if this higher priority ISR waits for a semaphore from a lower priority ISR, because the lower priority ISR can be preempted by the middle priority ISR. Priority inheritance is an effective protection method against this priority inversion problem, and it is expected to improve real-time performance of OS-less embedded systems. This paper proposes an ISR-callable priority inheritance semaphore which protects ISRs from priority inversion using hardware interrupt mechanism.
| Original language | English |
|---|---|
| Journal | IEEJ Transactions on Electronics, Information and Systems |
| Volume | 133 |
| Issue number | 11 |
| DOIs | |
| Publication status | Published - Jan 1 2013 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
A priority inherit semaphore mechanism of interrupt service routine using hardware interrupt level. / Nankaku, Shigeki; Kawakami, Hiroyuki; Koizumi, Hisao; Fukuda, Akira.
In: IEEJ Transactions on Electronics, Information and Systems, Vol. 133, No. 11, 01.01.2013.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A priority inherit semaphore mechanism of interrupt service routine using hardware interrupt level
AU - Nankaku, Shigeki
AU - Kawakami, Hiroyuki
AU - Koizumi, Hisao
AU - Fukuda, Akira
PY - 2013/1/1
Y1 - 2013/1/1
N2 - For embedded systems, concurrency is required to respond to various changes in real world. Real-time processing is required also, because the response typically has a time limit. The concurrency is implemented by processing Tasks or Interrupt Service Routines (ISRs) concurrently. And the necessity of mutual exclusion arises in concurrent processing, to maintain integrity of shared data. Task execution is scheduled by Real-time OS (RTOS), and mutual exclusion is serviced by semaphore. However approximately 30% of embedded systems do not use RTOS. These systems have no notion of Tasks, and are purely driven by ISRs. As the sole mutual exclusion method between ISRs, a pair of interrupt disable/enable instructions provided by CPU is used in these systems. This method enables a lower priority ISR to protect its critical section from higher priority ISRs, but it also defers execution of unrelated ISRs as it disables all external interrupts. We have resolved this timing issue with an ISR-callable semaphore, but that design was not priority inversion safe. Namely a middle priority ISR may indirectly block a higher priority ISR if this higher priority ISR waits for a semaphore from a lower priority ISR, because the lower priority ISR can be preempted by the middle priority ISR. Priority inheritance is an effective protection method against this priority inversion problem, and it is expected to improve real-time performance of OS-less embedded systems. This paper proposes an ISR-callable priority inheritance semaphore which protects ISRs from priority inversion using hardware interrupt mechanism.
AB - For embedded systems, concurrency is required to respond to various changes in real world. Real-time processing is required also, because the response typically has a time limit. The concurrency is implemented by processing Tasks or Interrupt Service Routines (ISRs) concurrently. And the necessity of mutual exclusion arises in concurrent processing, to maintain integrity of shared data. Task execution is scheduled by Real-time OS (RTOS), and mutual exclusion is serviced by semaphore. However approximately 30% of embedded systems do not use RTOS. These systems have no notion of Tasks, and are purely driven by ISRs. As the sole mutual exclusion method between ISRs, a pair of interrupt disable/enable instructions provided by CPU is used in these systems. This method enables a lower priority ISR to protect its critical section from higher priority ISRs, but it also defers execution of unrelated ISRs as it disables all external interrupts. We have resolved this timing issue with an ISR-callable semaphore, but that design was not priority inversion safe. Namely a middle priority ISR may indirectly block a higher priority ISR if this higher priority ISR waits for a semaphore from a lower priority ISR, because the lower priority ISR can be preempted by the middle priority ISR. Priority inheritance is an effective protection method against this priority inversion problem, and it is expected to improve real-time performance of OS-less embedded systems. This paper proposes an ISR-callable priority inheritance semaphore which protects ISRs from priority inversion using hardware interrupt mechanism.
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U2 - 10.1541/ieejeiss.133.2053
DO - 10.1541/ieejeiss.133.2053
M3 - Article
VL - 133
JO - IEEJ Transactions on Electronics, Information and Systems
JF - IEEJ Transactions on Electronics, Information and Systems
SN - 0385-4221
IS - 11
ER -