A reconfigurable functional unit for an adaptive dynamic extensible processor

Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Inoue Koji, Morteza Sahebzamani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication. The custom instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs are executed on the RFU. A quantitative approach was used for designing the RFU. The RFU is a matrix of functional units with 8 inputs and 6 outputs. Performance is enhanced up to 1.25 using the proposed RFU for 22 applications of Mibench. This processor needs no extra opcodes for CIs, new compiler, source code modification and recompilation.

Original languageEnglish
Title of host publicationProceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
Pages781-784
Number of pages4
DOIs
Publication statusPublished - Dec 1 2006
Event2006 International Conference on Field Programmable Logic and Applications, FPL - Madrid, Spain
Duration: Aug 28 2006Aug 30 2006

Publication series

NameProceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2006 International Conference on Field Programmable Logic and Applications, FPL
CountrySpain
CityMadrid
Period8/28/068/30/06

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Fabrication

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

Cite this

Noori, H., Mehdipour, F., Murakami, K., Koji, I., & Sahebzamani, M. (2006). A reconfigurable functional unit for an adaptive dynamic extensible processor. In Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL (pp. 781-784). [4101075] (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL). https://doi.org/10.1109/FPL.2006.311313

A reconfigurable functional unit for an adaptive dynamic extensible processor. / Noori, Hamid; Mehdipour, Farhad; Murakami, Kazuaki; Koji, Inoue; Sahebzamani, Morteza.

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. 2006. p. 781-784 4101075 (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Noori, H, Mehdipour, F, Murakami, K, Koji, I & Sahebzamani, M 2006, A reconfigurable functional unit for an adaptive dynamic extensible processor. in Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL., 4101075, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, pp. 781-784, 2006 International Conference on Field Programmable Logic and Applications, FPL, Madrid, Spain, 8/28/06. https://doi.org/10.1109/FPL.2006.311313
Noori H, Mehdipour F, Murakami K, Koji I, Sahebzamani M. A reconfigurable functional unit for an adaptive dynamic extensible processor. In Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. 2006. p. 781-784. 4101075. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL). https://doi.org/10.1109/FPL.2006.311313
Noori, Hamid ; Mehdipour, Farhad ; Murakami, Kazuaki ; Koji, Inoue ; Sahebzamani, Morteza. / A reconfigurable functional unit for an adaptive dynamic extensible processor. Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. 2006. pp. 781-784 (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).
@inproceedings{159d29cd702a4a15b6a16d1de453d62c,
title = "A reconfigurable functional unit for an adaptive dynamic extensible processor",
abstract = "This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication. The custom instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs are executed on the RFU. A quantitative approach was used for designing the RFU. The RFU is a matrix of functional units with 8 inputs and 6 outputs. Performance is enhanced up to 1.25 using the proposed RFU for 22 applications of Mibench. This processor needs no extra opcodes for CIs, new compiler, source code modification and recompilation.",
author = "Hamid Noori and Farhad Mehdipour and Kazuaki Murakami and Inoue Koji and Morteza Sahebzamani",
year = "2006",
month = "12",
day = "1",
doi = "10.1109/FPL.2006.311313",
language = "English",
isbn = "142440312X",
series = "Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL",
pages = "781--784",
booktitle = "Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL",

}

TY - GEN

T1 - A reconfigurable functional unit for an adaptive dynamic extensible processor

AU - Noori, Hamid

AU - Mehdipour, Farhad

AU - Murakami, Kazuaki

AU - Koji, Inoue

AU - Sahebzamani, Morteza

PY - 2006/12/1

Y1 - 2006/12/1

N2 - This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication. The custom instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs are executed on the RFU. A quantitative approach was used for designing the RFU. The RFU is a matrix of functional units with 8 inputs and 6 outputs. Performance is enhanced up to 1.25 using the proposed RFU for 22 applications of Mibench. This processor needs no extra opcodes for CIs, new compiler, source code modification and recompilation.

AB - This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication. The custom instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs are executed on the RFU. A quantitative approach was used for designing the RFU. The RFU is a matrix of functional units with 8 inputs and 6 outputs. Performance is enhanced up to 1.25 using the proposed RFU for 22 applications of Mibench. This processor needs no extra opcodes for CIs, new compiler, source code modification and recompilation.

UR - http://www.scopus.com/inward/record.url?scp=38749127791&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=38749127791&partnerID=8YFLogxK

U2 - 10.1109/FPL.2006.311313

DO - 10.1109/FPL.2006.311313

M3 - Conference contribution

SN - 142440312X

SN - 9781424403127

T3 - Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

SP - 781

EP - 784

BT - Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

ER -