A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits

Taiga Takata, Yusuke Matsunaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Analyzing logic masking effects in combinational circuits is an important key to evaluate soft error tolerance of circuits. Logic masking effects can be analyzed exactly with employing fault simulation. The computing complexity of a fault-simulation-based algorithm, however, is proportional to the square of circuit size, which might be unacceptable to achieve a scalable analyzer. On the other hand, a heuristic algorithm AnSER can analyze logic masking effects approximately in runtime proportional to circuit size. AnSER, however, is possible to analyze logic masking effects optimistically especially for circuits protected with spatial redundancy, which might not be suitable for soft error tolerant designs. This paper shows a robust algorithm to analyze logic masking effects pessimistically. Pessimistic analysis is guaranteed with employing the proposed algorithm, while the computing complexity of the proposed algorithm is proportional to circuit size. Experimental results show that the proposed algorithm runs about 91 times faster than a fault-simulation-based exact algorithm with 11.5% overestimate for average susceptibility to errors. For circuits partially protected with spatial redundancy, the proposed algorithm has estimated average susceptibility with 37.9% overestimates on average, while AnSER has estimated average susceptibility with 96% underestimates on average.

Original languageEnglish
Title of host publicationProceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011
Pages246-251
Number of pages6
DOIs
Publication statusPublished - Sep 19 2011
Event2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 - Athens, Greece
Duration: Jul 13 2011Jul 15 2011

Other

Other2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011
CountryGreece
CityAthens
Period7/13/117/15/11

Fingerprint

Combinatorial circuits
Networks (circuits)
Redundancy
Heuristic algorithms

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Takata, T., & Matsunaga, Y. (2011). A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. In Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 (pp. 246-251). [5994537] https://doi.org/10.1109/IOLTS.2011.5994537

A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. / Takata, Taiga; Matsunaga, Yusuke.

Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. p. 246-251 5994537.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Takata, T & Matsunaga, Y 2011, A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. in Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011., 5994537, pp. 246-251, 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, Athens, Greece, 7/13/11. https://doi.org/10.1109/IOLTS.2011.5994537
Takata T, Matsunaga Y. A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. In Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. p. 246-251. 5994537 https://doi.org/10.1109/IOLTS.2011.5994537
Takata, Taiga ; Matsunaga, Yusuke. / A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. pp. 246-251
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