## Abstract

Analyzing logic masking effects in combinational circuits is an important key to evaluate soft error tolerance of circuits. Logic masking effects can be analyzed exactly with employing fault simulation. The computing complexity of a fault-simulation-based algorithm, however, is proportional to the square of circuit size, which might be unacceptable to achieve a scalable analyzer. On the other hand, a heuristic algorithm AnSER can analyze logic masking effects approximately in runtime proportional to circuit size. AnSER, however, is possible to analyze logic masking effects optimistically especially for circuits protected with spatial redundancy, which might not be suitable for soft error tolerant designs. This paper shows a robust algorithm to analyze logic masking effects pessimistically. Pessimistic analysis is guaranteed with employing the proposed algorithm, while the computing complexity of the proposed algorithm is proportional to circuit size. Experimental results show that the proposed algorithm runs about 91 times faster than a fault-simulation-based exact algorithm with 11.5% overestimate for average susceptibility to errors. For circuits partially protected with spatial redundancy, the proposed algorithm has estimated average susceptibility with 37.9% overestimates on average, while AnSER has estimated average susceptibility with 96% underestimates on average.

Original language | English |
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Title of host publication | Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 |

Pages | 246-251 |

Number of pages | 6 |

DOIs | |

Publication status | Published - Sept 19 2011 |

Event | 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 - Athens, Greece Duration: Jul 13 2011 → Jul 15 2011 |

### Other

Other | 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 |
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Country/Territory | Greece |

City | Athens |

Period | 7/13/11 → 7/15/11 |

## All Science Journal Classification (ASJC) codes

- Electrical and Electronic Engineering