A selective replacement method for timing-error-predicting flip-flops

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshiba's MeP and Renesas Electronics's M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.

Original languageEnglish
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
Publication statusPublished - Oct 13 2011
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: Aug 7 2011Aug 10 2011

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period8/7/118/10/11

Fingerprint

Flip flop circuits
Redundancy
Transistors
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kunitake, Y., Sato, T., Yasuura, H., & Hayashida, T. (2011). A selective replacement method for timing-error-predicting flip-flops. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026267] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026267

A selective replacement method for timing-error-predicting flip-flops. / Kunitake, Yuji; Sato, Toshinori; Yasuura, Hiroto; Hayashida, Takanori.

54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026267 (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kunitake, Y, Sato, T, Yasuura, H & Hayashida, T 2011, A selective replacement method for timing-error-predicting flip-flops. in 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026267, Midwest Symposium on Circuits and Systems, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, Korea, Republic of, 8/7/11. https://doi.org/10.1109/MWSCAS.2011.6026267
Kunitake Y, Sato T, Yasuura H, Hayashida T. A selective replacement method for timing-error-predicting flip-flops. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026267. (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026267
Kunitake, Yuji ; Sato, Toshinori ; Yasuura, Hiroto ; Hayashida, Takanori. / A selective replacement method for timing-error-predicting flip-flops. 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. (Midwest Symposium on Circuits and Systems).
@inproceedings{199c9f54b7c943c3a77da0b2f7b6cbe2,
title = "A selective replacement method for timing-error-predicting flip-flops",
abstract = "The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshiba's MeP and Renesas Electronics's M32R. In the case of MeP, the area overhead is reduced from 55{\%} to 11{\%}.",
author = "Yuji Kunitake and Toshinori Sato and Hiroto Yasuura and Takanori Hayashida",
year = "2011",
month = "10",
day = "13",
doi = "10.1109/MWSCAS.2011.6026267",
language = "English",
isbn = "9781612848570",
series = "Midwest Symposium on Circuits and Systems",
booktitle = "54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011",

}

TY - GEN

T1 - A selective replacement method for timing-error-predicting flip-flops

AU - Kunitake, Yuji

AU - Sato, Toshinori

AU - Yasuura, Hiroto

AU - Hayashida, Takanori

PY - 2011/10/13

Y1 - 2011/10/13

N2 - The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshiba's MeP and Renesas Electronics's M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.

AB - The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshiba's MeP and Renesas Electronics's M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.

UR - http://www.scopus.com/inward/record.url?scp=80053630793&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80053630793&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2011.6026267

DO - 10.1109/MWSCAS.2011.6026267

M3 - Conference contribution

SN - 9781612848570

T3 - Midwest Symposium on Circuits and Systems

BT - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011

ER -