With the recent increases in data bandwidth, frequency and chip area in VLSI systems, the design methodology for on-chip clock distribution lines has been changing from an RC-model to an RLC-model and they must be treated as transmission lines. However, on-chip transmission line design requires time-consuming electromagnetic (EM) simulation and it is difficult to optimize many parameters such as metal width, space, length and layers within the limited time range. In this paper, we present a fully calculation-based on-chip transmission line modeling and optimization methodology. We applied our proposed methodology to a 9 mm on-chip clock distribution line with various metal layer combinations at 3 GHz in the TSMC 0.18 μm 1-poly 6-metal CMOS fabrication process. The generated model showed good match with EM-simulation. We also show that the optimization methodology can find the smallest metal width and space combination that achieves the lowest power from given target specifications such as delay and output swing.
All Science Journal Classification (ASJC) codes
- Physics and Astronomy(all)