A simple methodology for on-chip transmission line modeling and optimization for high-speed clock distribution

Translated title of the contribution: A simple methodology for on-chip transmission line modeling and optimization for high-speed clock distribution

Masahiro Ichihashi, Haruichi Kanaya

Research output: Contribution to journal › Article › peer-review

Translated title of the contribution	A simple methodology for on-chip transmission line modeling and optimization for high-speed clock distribution
Original language	Undefined/Unknown
Pages (from-to)	SBBC06-SBBC06
Journal	Japanese Journal of Applied Physics, Part 2: Letters
Volume	58
Issue number	0
Publication status	Published - Mar 27 2019

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title = "A simple methodology for on-chip transmission line modeling and optimization for high-speed clock distribution",

author = "Masahiro Ichihashi and Haruichi Kanaya",

year = "2019",

month = mar,

day = "27",

language = "未定義/不明",

volume = "58",

pages = "SBBC06--SBBC06",

journal = "Japanese Journal of Applied Physics, Part 2: Letters",

issn = "0021-4922",

publisher = "IOP Publishing Ltd.",

number = "0",

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TY - JOUR

T1 - A simple methodology for on-chip transmission line modeling and optimization for high-speed clock distribution

AU - Ichihashi, Masahiro

AU - Kanaya, Haruichi

PY - 2019/3/27

Y1 - 2019/3/27

M3 - 学術誌

SN - 0021-4922

VL - 58

SP - SBBC06-SBBC06

JO - Japanese Journal of Applied Physics, Part 2: Letters

JF - Japanese Journal of Applied Physics, Part 2: Letters

IS - 0

ER -