A small die area and high linearity 10-bit capacitive three-level DAC

Keigo Oshiro, Daisuke Kanemoto, Haruichi Kanaya, Ramesh Pokharel, Keiji Yoshida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A 10-bit capacitive three-level digital-to-analog converter (TLDAC) is provided to reduce differential non-linearity (DNL) and integral non-linearity (INL) caused by capacitive mismatch. The simulation results of binary-weighted TLDAC show 50 % reduction in DNL and INL compared to conventional binary-weighted DAC. Furthermore an additional reference voltage source has been reduced due to the advantages of differential circuit. The proposed 10-bit differential TLDAC was implemented in 0.18 μm CMOS process and its total area is 0.081 mm2.

Original languageEnglish
Title of host publication2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Pages164-167
Number of pages4
DOIs
Publication statusPublished - Dec 1 2012
Event2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan, Province of China
Duration: Dec 2 2012Dec 5 2012

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
CountryTaiwan, Province of China
CityKaohsiung
Period12/2/1212/5/12

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Oshiro, K., Kanemoto, D., Kanaya, H., Pokharel, R., & Yoshida, K. (2012). A small die area and high linearity 10-bit capacitive three-level DAC. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 (pp. 164-167). [6418997] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2012.6418997