A soft error tolerance estimation method for sequential circuits

Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In advanced technology, soft error tolerance of VLSIs decreases. Soft errors might cause VLSIs to failure. However, there is no exact method to estimate soft error tolerance for sequential circuits of VLSIs. We propose an exact method to estimate soft error tolerance for sequential circuits. The failure due to soft errors in sequential circuits is defined by using the modified product machine. The behavior of the modified product machine is analyzed using Markov model strictly. We also propose two acceleration techniques to apply the exact method to larger scale circuits. Two acceleration techniques reduce the number of variables of simultaneous linear equations. We apply the proposed method to ISCAS'89 and MCNC benchmark circuits and estimate soft error tolerance for sequential circuits. Experimental results shows that two acceleration techniques reduce up to 10 times from its original execution time.

Original languageEnglish
Title of host publicationProceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
Pages268-276
Number of pages9
DOIs
Publication statusPublished - Dec 1 2011
Event2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011 - Vancouver, BC, Canada
Duration: Oct 3 2011Oct 5 2011

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Other

Other2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
CountryCanada
CityVancouver, BC
Period10/3/1110/5/11

Fingerprint

Sequential circuits
Networks (circuits)
Linear equations

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Yoshimura, M., Akamine, Y., & Matsunaga, Y. (2011). A soft error tolerance estimation method for sequential circuits. In Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011 (pp. 268-276). [6104452] (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2011.22

A soft error tolerance estimation method for sequential circuits. / Yoshimura, Masayoshi; Akamine, Yusuke; Matsunaga, Yusuke.

Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011. 2011. p. 268-276 6104452 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoshimura, M, Akamine, Y & Matsunaga, Y 2011, A soft error tolerance estimation method for sequential circuits. in Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011., 6104452, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 268-276, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, 10/3/11. https://doi.org/10.1109/DFT.2011.22
Yoshimura M, Akamine Y, Matsunaga Y. A soft error tolerance estimation method for sequential circuits. In Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011. 2011. p. 268-276. 6104452. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2011.22
Yoshimura, Masayoshi ; Akamine, Yusuke ; Matsunaga, Yusuke. / A soft error tolerance estimation method for sequential circuits. Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011. 2011. pp. 268-276 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).
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