A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation

Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may even change position with changes in the operating voltage and temperature, and hence, redundancy at circuit-level is not sufficient to tolerate such threats to yield. We show that in SRAM cells this leakage depends on the cell value and propose a first software-based runtime technique that suppresses such abnormal leakages by storing safe values in the corresponding cache lines before going to standby mode. Analysis shows the performance penalty is, in the worst case, linearly dependent to the number of so-cured cache lines while the energy saving linearly increases by the time spent in standby mode. Analysis and experimental results on commercial processors confirm that the technique is viable if the standby duration is more than a small fraction of a second.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages878-883
Number of pages6
DOIs
Publication statusPublished - Dec 1 2007
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: Jan 23 2007Jan 27 2007

Other

OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
CountryJapan
CityYokohama
Period1/23/071/27/07

Fingerprint

Static random access storage
Transistors
Threshold voltage
Redundancy
Energy conservation
Networks (circuits)
Electric potential
Temperature

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Goudarzi, M., Ishihara, T., & Yasuura, H. (2007). A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 (pp. 878-883). [4196146] https://doi.org/10.1109/ASPDAC.2007.358100

A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation. / Goudarzi, Maziar; Ishihara, Tohru; Yasuura, Hiroto.

Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. p. 878-883 4196146.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Goudarzi, M, Ishihara, T & Yasuura, H 2007, A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation. in Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007., 4196146, pp. 878-883, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, 1/23/07. https://doi.org/10.1109/ASPDAC.2007.358100
Goudarzi M, Ishihara T, Yasuura H. A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. p. 878-883. 4196146 https://doi.org/10.1109/ASPDAC.2007.358100
Goudarzi, Maziar ; Ishihara, Tohru ; Yasuura, Hiroto. / A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation. Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. pp. 878-883
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