A study of capture-safe test generation flow for at-speed testing

Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja

Research output: Contribution to journalArticle

Abstract

Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.

Original languageEnglish
Pages (from-to)1309-1318
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE93-A
Issue number7
DOIs
Publication statusPublished - Jan 1 2010

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All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Electrical and Electronic Engineering

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