Abstract
This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.
| Original language | English |
|---|---|
| Pages (from-to) | 2302-2309 |
| Number of pages | 8 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E99A |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - Dec 2016 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics
Cite this
A test pattern compaction method using SAT-based fault grouping. / Matsunaga, Yusuke.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E99A, No. 12, 12.2016, p. 2302-2309.Research output: Contribution to journal › Article
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TY - JOUR
T1 - A test pattern compaction method using SAT-based fault grouping
AU - Matsunaga, Yusuke
PY - 2016/12
Y1 - 2016/12
N2 - This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.
AB - This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.
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U2 - 10.1587/transfun.E99.A.2302
DO - 10.1587/transfun.E99.A.2302
M3 - Article
AN - SCOPUS:84999273621
VL - E99A
SP - 2302
EP - 2309
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 12
ER -