A test pattern compaction method using SAT-based fault grouping

Yusuke Matsunaga

doi:10.1587/transfun.E99.A.2302

A test pattern compaction method using SAT-based fault grouping

Yusuke Matsunaga

Advanced Inormation and Communication Technology

Research output: Contribution to journal › Article › peer-review

Abstract

This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.

Original language	English
Pages (from-to)	2302-2309
Number of pages	8
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E99A
Issue number	12
DOIs	https://doi.org/10.1587/transfun.E99.A.2302
Publication status	Published - Dec 2016

All Science Journal Classification (ASJC) codes

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

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10.1587/transfun.E99.A.2302

Cite this

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A test pattern compaction method using SAT-based fault grouping

Abstract

All Science Journal Classification (ASJC) codes

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