A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS

Ghazal Fahmy, Daisuke Kanemoto, Haruichi Kanaya, Keiji Yoshida, Ramesh Pokharel, Awinash Anand

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.

Original languageEnglish
Pages (from-to)1204-1209
Number of pages6
JournalIEICE Electronics Express
Volume8
Issue number15
DOIs
Publication statusPublished - Aug 10 2011

Fingerprint

Operational amplifiers
Modulators
modulators
CMOS
integrators
analog to digital converters
transmitter receivers
sampling
bandwidth
filters
high resolution
Digital to analog conversion
Transceivers
Electric power utilization
Sampling
Bandwidth
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS. / Fahmy, Ghazal; Kanemoto, Daisuke; Kanaya, Haruichi; Yoshida, Keiji; Pokharel, Ramesh; Anand, Awinash.

In: IEICE Electronics Express, Vol. 8, No. 15, 10.08.2011, p. 1204-1209.

Research output: Contribution to journalArticle

Fahmy, Ghazal ; Kanemoto, Daisuke ; Kanaya, Haruichi ; Yoshida, Keiji ; Pokharel, Ramesh ; Anand, Awinash. / A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS. In: IEICE Electronics Express. 2011 ; Vol. 8, No. 15. pp. 1204-1209.
@article{596cfc3f05be45e0941b205e25c9afc8,
title = "A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS",
abstract = "Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.",
author = "Ghazal Fahmy and Daisuke Kanemoto and Haruichi Kanaya and Keiji Yoshida and Ramesh Pokharel and Awinash Anand",
year = "2011",
month = "8",
day = "10",
doi = "10.1587/elex.8.1204",
language = "English",
volume = "8",
pages = "1204--1209",
journal = "IEICE Electronics Express",
issn = "1349-2543",
publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
number = "15",

}

TY - JOUR

T1 - A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS

AU - Fahmy, Ghazal

AU - Kanemoto, Daisuke

AU - Kanaya, Haruichi

AU - Yoshida, Keiji

AU - Pokharel, Ramesh

AU - Anand, Awinash

PY - 2011/8/10

Y1 - 2011/8/10

N2 - Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.

AB - Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.

UR - http://www.scopus.com/inward/record.url?scp=80052542464&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052542464&partnerID=8YFLogxK

U2 - 10.1587/elex.8.1204

DO - 10.1587/elex.8.1204

M3 - Article

AN - SCOPUS:80052542464

VL - 8

SP - 1204

EP - 1209

JO - IEICE Electronics Express

JF - IEICE Electronics Express

SN - 1349-2543

IS - 15

ER -