A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS

Ghazal Fahmy; Daisuke Kanemoto; Haruichi Kanaya; Keiji Yoshida; Ramesh Pokharel; Awinash Anand

doi:10.1587/elex.8.1204

A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS

Ghazal Fahmy, Daisuke Kanemoto, Haruichi Kanaya, Keiji Yoshida, Ramesh Pokharel, Awinash Anand

Research output: Contribution to journal › Article › peer-review

Abstract

Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.

Original language	English
Pages (from-to)	1204-1209
Number of pages	6
Journal	IEICE Electronics Express
Volume	8
Issue number	15
DOIs	https://doi.org/10.1587/elex.8.1204
Publication status	Published - 2011

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https://doi.org/10.1587/elex.8.1204

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title = "A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS",

abstract = "Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.",

author = "Ghazal Fahmy and Daisuke Kanemoto and Haruichi Kanaya and Keiji Yoshida and Ramesh Pokharel and Awinash Anand",

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AU - Fahmy, Ghazal

AU - Kanemoto, Daisuke

AU - Kanaya, Haruichi

AU - Yoshida, Keiji

AU - Pokharel, Ramesh

AU - Anand, Awinash

PY - 2011

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AB - Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.

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