Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (<i>DSM</i>) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on <i>TSMC</i> 0.18um <i>CMOS</i> technology. <i>2MHz</i> Bandwidth, 50dB Peak <i>SQNR</i>, which is suitable for <i>WCDMA</i>, have been achieved.