A thread-level parallelization of pairwise additive potential and force calculations suitable for current many-core architectures

Yoshimichi Ando, Soichiro Suzuki, Satoshi Ohshima, Tetsuya Sakashita, Masao Ogino, Takahiro Katagiri, Noriyuki Yoshii, Susumu Okazaki

Research output: Contribution to journalArticle

3 Citations (Scopus)
Original languageEnglish
JournalJournal of Supercomputing
DOIs
Publication statusPublished - Feb 12 2018

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