A three-dimensional integrated accelerator

Farhad Mehdipour, Krishna C. Nunna, Koji Inoue, Kazuaki J. Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.

Original languageEnglish
Title of host publicationProceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
Pages148-151
Number of pages4
DOIs
Publication statusPublished - Dec 1 2012
Event15th Euromicro Conference on Digital System Design, DSD 2012 - Cesme, Izmir, Turkey
Duration: Sep 5 2012Sep 8 2012

Publication series

NameProceedings - 15th Euromicro Conference on Digital System Design, DSD 2012

Other

Other15th Euromicro Conference on Digital System Design, DSD 2012
CountryTurkey
CityCesme, Izmir
Period9/5/129/8/12

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All Science Journal Classification (ASJC) codes

  • Information Systems

Cite this

Mehdipour, F., Nunna, K. C., Inoue, K., & Murakami, K. J. (2012). A three-dimensional integrated accelerator. In Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012 (pp. 148-151). [6386885] (Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012). https://doi.org/10.1109/DSD.2012.15