A three-dimensional integrated accelerator

Farhad Mehdipour; Krishna C. Nunna; Koji Inoue; Kazuaki J. Murakami

doi:10.1109/DSD.2012.15

A three-dimensional integrated accelerator

Farhad Mehdipour, Krishna C. Nunna, Koji Inoue, Kazuaki J. Murakami

Department of I&E Visionaries

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.

Original language	English
Title of host publication	Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
Pages	148-151
Number of pages	4
DOIs	https://doi.org/10.1109/DSD.2012.15
Publication status	Published - Dec 1 2012
Event	15th Euromicro Conference on Digital System Design, DSD 2012 - Cesme, Izmir, Turkey Duration: Sep 5 2012 → Sep 8 2012

Publication series

Name	Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012

Other

Other	15th Euromicro Conference on Digital System Design, DSD 2012
Country	Turkey
City	Cesme, Izmir
Period	9/5/12 → 9/8/12

All Science Journal Classification (ASJC) codes

Information Systems

Access to Document

10.1109/DSD.2012.15

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A three-dimensional integrated accelerator. / Mehdipour, Farhad; Nunna, Krishna C.; Inoue, Koji; Murakami, Kazuaki J.

Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012. 2012. p. 148-151 6386885 (Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Mehdipour, F, Nunna, KC, Inoue, K & Murakami, KJ 2012, A three-dimensional integrated accelerator. in Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012., 6386885, Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012, pp. 148-151, 15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, Turkey, 9/5/12. https://doi.org/10.1109/DSD.2012.15

@inproceedings{f28cb76fff374b4a940ec920b43f78e3,

title = "A three-dimensional integrated accelerator",

abstract = "We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.",

author = "Farhad Mehdipour and Nunna, {Krishna C.} and Koji Inoue and Murakami, {Kazuaki J.}",

year = "2012",

month = dec,

day = "1",

doi = "10.1109/DSD.2012.15",

language = "English",

isbn = "9780769547985",

series = "Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012",

pages = "148--151",

booktitle = "Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012",

note = "15th Euromicro Conference on Digital System Design, DSD 2012 ; Conference date: 05-09-2012 Through 08-09-2012",

}

TY - GEN

T1 - A three-dimensional integrated accelerator

AU - Mehdipour, Farhad

AU - Nunna, Krishna C.

AU - Inoue, Koji

AU - Murakami, Kazuaki J.

PY - 2012/12/1

Y1 - 2012/12/1

N2 - We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.

AB - We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.

UR - http://www.scopus.com/inward/record.url?scp=84872899359&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84872899359&partnerID=8YFLogxK

U2 - 10.1109/DSD.2012.15

DO - 10.1109/DSD.2012.15

M3 - Conference contribution

AN - SCOPUS:84872899359

SN - 9780769547985

T3 - Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012

SP - 148

EP - 151

BT - Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012

T2 - 15th Euromicro Conference on Digital System Design, DSD 2012

Y2 - 5 September 2012 through 8 September 2012

ER -