TY - GEN
T1 - A three-dimensional integrated accelerator
AU - Mehdipour, Farhad
AU - Nunna, Krishna C.
AU - Inoue, Koji
AU - Murakami, Kazuaki J.
PY - 2012/12/1
Y1 - 2012/12/1
N2 - We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.
AB - We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.
UR - http://www.scopus.com/inward/record.url?scp=84872899359&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84872899359&partnerID=8YFLogxK
U2 - 10.1109/DSD.2012.15
DO - 10.1109/DSD.2012.15
M3 - Conference contribution
AN - SCOPUS:84872899359
SN - 9780769547985
T3 - Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
SP - 148
EP - 151
BT - Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
T2 - 15th Euromicro Conference on Digital System Design, DSD 2012
Y2 - 5 September 2012 through 8 September 2012
ER -