Abstract
This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.
Original language | English |
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Title of host publication | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 34-35 |
Number of pages | 2 |
ISBN (Electronic) | 9781479977925 |
DOIs | |
Publication status | Published - Mar 11 2015 |
Event | 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: Jan 19 2015 → Jan 22 2015 |
Publication series
Name | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 |
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Other
Other | 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 |
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Country | Japan |
City | Chiba |
Period | 1/19/15 → 1/22/15 |
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All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering
- Control and Systems Engineering
- Modelling and Simulation
Cite this
A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. / Kanemoto, Daisuke; Oshiro, Keigo; Yoshida, Keiji; Kanaya, Haruichi.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 34-35 7058973 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications
AU - Kanemoto, Daisuke
AU - Oshiro, Keigo
AU - Yoshida, Keiji
AU - Kanaya, Haruichi
PY - 2015/3/11
Y1 - 2015/3/11
N2 - This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.
AB - This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.
UR - http://www.scopus.com/inward/record.url?scp=84926452899&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84926452899&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2015.7058973
DO - 10.1109/ASPDAC.2015.7058973
M3 - Conference contribution
AN - SCOPUS:84926452899
T3 - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
SP - 34
EP - 35
BT - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
ER -