A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications

Daisuke Kanemoto, Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.

Original languageEnglish
Title of host publication20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages34-35
Number of pages2
ISBN (Electronic)9781479977925
DOIs
Publication statusPublished - Mar 11 2015
Event2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
Duration: Jan 19 2015Jan 22 2015

Publication series

Name20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
CountryJapan
CityChiba
Period1/19/151/22/15

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modelling and Simulation

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    Kanemoto, D., Oshiro, K., Yoshida, K., & Kanaya, H. (2015). A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 34-35). [7058973] (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058973