A VLSI chip set for a large-scale parallel inference machine: PIM/m

Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Yamashita, Masao Nakaya, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masayoshi Sakao

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents three VLSI chips—a processor (PU) chip, a cache memory (CU) chip, and a network control (NU) chip—for a large-scale parallel inference machine. The PU chip has been designed to be adapted to logic programming languages such as Prolog. The CU chip implements a hardware support called “trail buffer” which is suitable for the execution of the Prolog-like languages. The NU chip makes it possible to connect 256 processing elements in a mesh network. The parallel inference machine (PIM/m) runs a Prolog-like network-based operating system called PIMOS as well as many applications and has a peak performance of 128 mega logical inferences per second (MLIPS). The PU chip containing 384 000 transistors is fabricated in a 0.8-μm double-metal CMOS technology. The CU chip and the NU chip contain 610 000 and 329 000 transistors, respectively. They are fabricated in a 1.0-μm double-metal CMOS technology. A cell-based design method is used to reduce the layout design time.

Original languageEnglish
Pages (from-to)344-351
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume28
Issue number3
DOIs
Publication statusPublished - Mar 1993
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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