A VLSI chip set for a large-scale parallel inference machine: PIM/m

Hirohisa Machida; Hideki Ando; Kenichi Yasuda; Kiyohiro Furutani; Yukihiro Yamashita; Masao Nakaya; Hiroshi Nakashima; Yasutaka Takeda; Katsuto Nakajima; Masayoshi Sakao

doi:10.1109/4.210002

A VLSI chip set for a large-scale parallel inference machine: PIM/m

Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Yamashita, Masao Nakaya, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masayoshi Sakao

Research output: Contribution to journal › Article › peer-review

Abstract

This paper presents three VLSI chips—a processor (PU) chip, a cache memory (CU) chip, and a network control (NU) chip—for a large-scale parallel inference machine. The PU chip has been designed to be adapted to logic programming languages such as Prolog. The CU chip implements a hardware support called “trail buffer” which is suitable for the execution of the Prolog-like languages. The NU chip makes it possible to connect 256 processing elements in a mesh network. The parallel inference machine (PIM/m) runs a Prolog-like network-based operating system called PIMOS as well as many applications and has a peak performance of 128 mega logical inferences per second (MLIPS). The PU chip containing 384 000 transistors is fabricated in a 0.8-μm double-metal CMOS technology. The CU chip and the NU chip contain 610 000 and 329 000 transistors, respectively. They are fabricated in a 1.0-μm double-metal CMOS technology. A cell-based design method is used to reduce the layout design time.

Original language	English
Pages (from-to)	344-351
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	28
Issue number	3
DOIs	https://doi.org/10.1109/4.210002
Publication status	Published - Mar 1993
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/4.210002

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A VLSI chip set for a large-scale parallel inference machine : PIM/m. / Machida, Hirohisa; Ando, Hideki; Yasuda, Kenichi; Furutani, Kiyohiro; Yamashita, Yukihiro; Nakaya, Masao; Nakashima, Hiroshi; Takeda, Yasutaka; Nakajima, Katsuto; Sakao, Masayoshi.

In: IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, 03.1993, p. 344-351.

Research output: Contribution to journal › Article › peer-review

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abstract = "This paper presents three VLSI chips—a processor (PU) chip, a cache memory (CU) chip, and a network control (NU) chip—for a large-scale parallel inference machine. The PU chip has been designed to be adapted to logic programming languages such as Prolog. The CU chip implements a hardware support called “trail buffer” which is suitable for the execution of the Prolog-like languages. The NU chip makes it possible to connect 256 processing elements in a mesh network. The parallel inference machine (PIM/m) runs a Prolog-like network-based operating system called PIMOS as well as many applications and has a peak performance of 128 mega logical inferences per second (MLIPS). The PU chip containing 384 000 transistors is fabricated in a 0.8-μm double-metal CMOS technology. The CU chip and the NU chip contain 610 000 and 329 000 transistors, respectively. They are fabricated in a 1.0-μm double-metal CMOS technology. A cell-based design method is used to reduce the layout design time.",

author = "Hirohisa Machida and Hideki Ando and Kenichi Yasuda and Kiyohiro Furutani and Yukihiro Yamashita and Masao Nakaya and Hiroshi Nakashima and Yasutaka Takeda and Katsuto Nakajima and Masayoshi Sakao",

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AU - Nakaya, Masao

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