A VLSI chip set for a large scale parallel inference machine: PIM/m

Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masao Nakaya

Research output: Contribution to journalConference articlepeer-review

Abstract

Three VLSI chips which are a processor chip, a cache memory chip, and a network control chip for a highly parallel inference machine with capability of max 128 MRPS (Mega Reduction Per Second) have been developed. A processing element (PE) which consists of the processor chip and the cache memory chip has been designed to be suited for logic programming languages. The processor chip has been constructed in a submicron CMOS process teclhnologies. The cache memory chip implements a hardware support called "Trail Buffer" which is suitable for the execution of the Prolog-like languages. The network control chip makes it possible to connect 256 PES in a mesh network.

Original languageEnglish
Article number5727431
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
Publication statusPublished - Dec 1 1992
Externally publishedYes
Event14th Annual Custom Integrated Circuits Conference, CICC 1992 - Boston, MA, United States
Duration: May 3 1992May 6 1992

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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