Abstract
This paper presents the design and implementation of 0.9-4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S11| less than-4.4 dB, and an output return loss |S22| less than-9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was-9dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.
| Original language | English |
|---|---|
| Pages (from-to) | 1182-1188 |
| Number of pages | 7 |
| Journal | IEICE Transactions on Electronics |
| Volume | E95-C |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - Jan 1 2012 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
A wide range CMOS power amplifier with improved group delay variation and gain flatness for UWB transmitters. / Sapawi, Rohana; Pokharel, Ramesh; Kanaya, Haruichi; Yoshida, Keiji.
In: IEICE Transactions on Electronics, Vol. E95-C, No. 7, 01.01.2012, p. 1182-1188.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A wide range CMOS power amplifier with improved group delay variation and gain flatness for UWB transmitters
AU - Sapawi, Rohana
AU - Pokharel, Ramesh
AU - Kanaya, Haruichi
AU - Yoshida, Keiji
PY - 2012/1/1
Y1 - 2012/1/1
N2 - This paper presents the design and implementation of 0.9-4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S11| less than-4.4 dB, and an output return loss |S22| less than-9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was-9dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.
AB - This paper presents the design and implementation of 0.9-4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S11| less than-4.4 dB, and an output return loss |S22| less than-9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was-9dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.
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U2 - 10.1587/transele.E95.C.1182
DO - 10.1587/transele.E95.C.1182
M3 - Article
AN - SCOPUS:84863444573
VL - E95-C
SP - 1182
EP - 1188
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
SN - 0916-8524
IS - 7
ER -