A wide tuning range CMOS quadrature ring oscillator with improved FoM for inductorless reconfigurable PLL

Ramesh K. Pokharel; Shashank Lingala; Awinash Anand; Prapto Nugroho; Abhishek Tomar; Haruichi Kanaya; Keiji Yoshida

doi:10.1587/transele.E94.C.1524

A wide tuning range CMOS quadrature ring oscillator with improved FoM for inductorless reconfigurable PLL

Ramesh K. Pokharel, Shashank Lingala, Awinash Anand, Prapto Nugroho, Abhishek Tomar, Haruichi Kanaya, Keiji Yoshida

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18 μm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise of -125.8 dBc/Hz at 4MHz offset from the carrier frequency of 3.4 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency tuning sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.

Original language	English
Pages (from-to)	1524-1532
Number of pages	9
Journal	IEICE Transactions on Electronics
Volume	E94-C
Issue number	10
DOIs	https://doi.org/10.1587/transele.E94.C.1524
Publication status	Published - Oct 2011

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1587/transele.E94.C.1524

Cite this

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title = "A wide tuning range CMOS quadrature ring oscillator with improved FoM for inductorless reconfigurable PLL",

abstract = "This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18 μm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise of -125.8 dBc/Hz at 4MHz offset from the carrier frequency of 3.4 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency tuning sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.",

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T1 - A wide tuning range CMOS quadrature ring oscillator with improved FoM for inductorless reconfigurable PLL

AU - Pokharel, Ramesh K.

AU - Lingala, Shashank

AU - Anand, Awinash

AU - Nugroho, Prapto

AU - Tomar, Abhishek

AU - Kanaya, Haruichi

AU - Yoshida, Keiji

PY - 2011/10

Y1 - 2011/10

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AB - This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18 μm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise of -125.8 dBc/Hz at 4MHz offset from the carrier frequency of 3.4 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency tuning sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.

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A wide tuning range CMOS quadrature ring oscillator with improved FoM for inductorless reconfigurable PLL

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