Achievement of low parasitic resistance in Ge n-channel metal-oxide-semiconductor field-effect transistor using an embedded TiN-source/drain structure

We investigated the source/drain (S/D) parasitic resistance (R _P) of a Ge n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) with TiN-S/D. The R _P was as high as ∼1400 Ω, which is attributed to a very thin amorphous interlayer (a-IL) at a TiN/Ge interface. To solve this problem, n-MOSFETs with an embedded S/D structure were fabricated, of which the S/D was formed by the etching of a Ge layer using 0.03%-H₂O₂ solution followed by TiN sputter deposition. The electrical performances were investigated for devices with etching depths in the range of 2-22 nm. The devices with etching depths of 2-5 nm did not work. The devices with etching depths of 12-15 nm showed a quite normal transistor operation, and the R _P was as low as ∼130 Ω, which is comparable to that of a p-MOSFET with PtGe-S/D. However, R _Ps of the devices with etching depths of ∼22 nm was considerably high. The reason for these results is discussed on the basis of an a-IL formation at the sidewall of the engraved S/D region.