TY - JOUR
T1 - Achievement of low parasitic resistance in Ge n-channel metal-oxide-semiconductor field-effect transistor using an embedded TiN-source/drain structure
AU - Nagatomi, Y.
AU - Tateyama, T.
AU - Tanaka, S.
AU - Yamamoto, K.
AU - Wang, D.
AU - Nakashima, H.
N1 - Funding Information:
his work was supported by (JSPS) KAKENHI (grant numbers 25249035 and 26289090) and was partially supported by JSPS Core-to-Core Program, A. Advanced Research Networks.
Publisher Copyright:
© 2017 IOP Publishing Ltd.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2017/1/24
Y1 - 2017/1/24
N2 - We investigated the source/drain (S/D) parasitic resistance (R P) of a Ge n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) with TiN-S/D. The R P was as high as ∼1400 Ω, which is attributed to a very thin amorphous interlayer (a-IL) at a TiN/Ge interface. To solve this problem, n-MOSFETs with an embedded S/D structure were fabricated, of which the S/D was formed by the etching of a Ge layer using 0.03%-H2O2 solution followed by TiN sputter deposition. The electrical performances were investigated for devices with etching depths in the range of 2-22 nm. The devices with etching depths of 2-5 nm did not work. The devices with etching depths of 12-15 nm showed a quite normal transistor operation, and the R P was as low as ∼130 Ω, which is comparable to that of a p-MOSFET with PtGe-S/D. However, R Ps of the devices with etching depths of ∼22 nm was considerably high. The reason for these results is discussed on the basis of an a-IL formation at the sidewall of the engraved S/D region.
AB - We investigated the source/drain (S/D) parasitic resistance (R P) of a Ge n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) with TiN-S/D. The R P was as high as ∼1400 Ω, which is attributed to a very thin amorphous interlayer (a-IL) at a TiN/Ge interface. To solve this problem, n-MOSFETs with an embedded S/D structure were fabricated, of which the S/D was formed by the etching of a Ge layer using 0.03%-H2O2 solution followed by TiN sputter deposition. The electrical performances were investigated for devices with etching depths in the range of 2-22 nm. The devices with etching depths of 2-5 nm did not work. The devices with etching depths of 12-15 nm showed a quite normal transistor operation, and the R P was as low as ∼130 Ω, which is comparable to that of a p-MOSFET with PtGe-S/D. However, R Ps of the devices with etching depths of ∼22 nm was considerably high. The reason for these results is discussed on the basis of an a-IL formation at the sidewall of the engraved S/D region.
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U2 - 10.1088/1361-6641/32/3/035001
DO - 10.1088/1361-6641/32/3/035001
M3 - Article
AN - SCOPUS:85014541631
VL - 32
JO - Semiconductor Science and Technology
JF - Semiconductor Science and Technology
SN - 0268-1242
IS - 3
M1 - 035001
ER -