Achievement of ultralow contact resistivity of metal/n+-ge contacts with Zr-N-Ge amorphous interlayer

Hiroshi Nakashima, Hayalo Okamoto, Keisuke Yamamoto, Dong Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


A bottleneck for achieving Gc-CMOS is the Fermi-level pinning (FLP) phenomenon, which causes high electron barrier height (Obn) for metal/Ge contacts, resulting in an increase in contact resistivity (ρc) between metal and n+-source/drain for n-MOSFET. We have found that the low Φbn can be realized by directly sputtered TiN/Ge and ZrN/Ge contacts, which is induced by amorphous interlayer (a-IL) formed during the sputter deposition. In this paper, we present that the a-IL in the ZrN/Ge contact can be retained on Ge surface, which enables us to fabricate metal/a-IL/Ge contacts with different metals. We investigated the electrical properties of metal/a-IL/Gc and metal/a-IL/n+-Ge contacts and showed that the a-IL remarkably modulate the Φbn and ρc. As a result, we succeeded in ultralow ρc for Ag/a-IL/n+-Ge with post metallization annealing at 400°C, which was an average ρc value of 2×10-7 ω·cm2

Original languageEnglish
Title of host publicationECS Transactions
EditorsK. Shiojima, A. Mai, J. Murota, P. Chin, C. L. Claeys, H. Iwai, S. Deleonibus, M. Tao
PublisherElectrochemical Society Inc.
Number of pages10
ISBN (Electronic)9781607685395
Publication statusPublished - 2017
Event10th Symposium on Semiconductor Process Integration - 232nd ECS Meeting - National Harbor, United States
Duration: Oct 1 2017Oct 5 2017

Publication series

NameECS Transactions
ISSN (Print)1938-6737
ISSN (Electronic)1938-5862


Other10th Symposium on Semiconductor Process Integration - 232nd ECS Meeting
CountryUnited States
CityNational Harbor

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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