Abstract
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system's performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.
| Original language | English |
|---|---|
| Pages (from-to) | 32-37 |
| Number of pages | 6 |
| Journal | Proceedings of the International Symposium on System Synthesis |
| Publication status | Published - Dec 1 2002 |
| Event | 15th International Symposium on System Synthesis - Kyoto, Japan Duration: Oct 2 2002 → Oct 4 2002 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
Cite this
An accelerated datapath width optimization scheme for area reduction of embedded systems. / Uddin, Mohammad Mesbah; Cao, Yun; Yasuura, Hiroto.
In: Proceedings of the International Symposium on System Synthesis, 01.12.2002, p. 32-37.Research output: Contribution to journal › Conference article
}
TY - JOUR
T1 - An accelerated datapath width optimization scheme for area reduction of embedded systems
AU - Uddin, Mohammad Mesbah
AU - Cao, Yun
AU - Yasuura, Hiroto
PY - 2002/12/1
Y1 - 2002/12/1
N2 - Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system's performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.
AB - Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system's performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.
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UR - http://www.scopus.com/inward/citedby.url?scp=0036949042&partnerID=8YFLogxK
M3 - Conference article
SP - 32
EP - 37
JO - Proceedings of the International Symposium on System Synthesis
JF - Proceedings of the International Symposium on System Synthesis
SN - 1080-1820
ER -