An accelerated datapath width optimization scheme for area reduction of embedded systems

Mohammad Mesbah Uddin, Yun Cao, Hiroto Yasuura

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system's performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.

Original languageEnglish
Pages (from-to)32-37
Number of pages6
JournalProceedings of the International Symposium on System Synthesis
Publication statusPublished - Dec 1 2002
Event15th International Symposium on System Synthesis - Kyoto, Japan
Duration: Oct 2 2002Oct 4 2002

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Embedded systems

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

An accelerated datapath width optimization scheme for area reduction of embedded systems. / Uddin, Mohammad Mesbah; Cao, Yun; Yasuura, Hiroto.

In: Proceedings of the International Symposium on System Synthesis, 01.12.2002, p. 32-37.

Research output: Contribution to journalConference article

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