TY - JOUR
T1 - An accelerated datapath width optimization scheme for area reduction of embedded systems
AU - Uddin, Mohammad Mesbah
AU - Cao, Yun
AU - Yasuura, Hiroto
N1 - Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2002
Y1 - 2002
N2 - Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system's performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.
AB - Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system's performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.
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U2 - 10.1145/581202.581208
DO - 10.1145/581202.581208
M3 - Conference article
AN - SCOPUS:0036949042
SP - 32
EP - 37
JO - Proceedings of the International Symposium on System Synthesis
JF - Proceedings of the International Symposium on System Synthesis
SN - 1080-1820
T2 - 15th International Symposium on System Synthesis
Y2 - 2 October 2002 through 4 October 2002
ER -