Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system's performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.
|Number of pages||6|
|Journal||Proceedings of the International Symposium on System Synthesis|
|Publication status||Published - 2002|
|Event||15th International Symposium on System Synthesis - Kyoto, Japan|
Duration: Oct 2 2002 → Oct 4 2002
All Science Journal Classification (ASJC) codes
- Hardware and Architecture