This paper describes an accelerating technique for SAT based ATPG (automatic test pattern generation). The main idea of the proposed algorithm is representing more than one test generation problems as one CNF formula with introducing control variables, which reduces CNF generation time. Furthermore, learnt clauses of previously solved problems are effectively shared for other problems solving, so that the SAT solving time is also reduced. Experimental results show that the proposed algorithm runs more than 3 times faster than the original SAT-based ATPG algorithm.
|Number of pages||6|
|Journal||IPSJ Transactions on System LSI Design Methodology|
|Publication status||Published - Feb 2017|
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering