An accelerating technique for SAT-based ATPG

Research output: Contribution to journalArticle

Abstract

This paper describes an accelerating technique for SAT based ATPG (automatic test pattern generation). The main idea of the proposed algorithm is representing more than one test generation problems as one CNF formula with introducing control variables, which reduces CNF generation time. Furthermore, learnt clauses of previously solved problems are effectively shared for other problems solving, so that the SAT solving time is also reduced. Experimental results show that the proposed algorithm runs more than 3 times faster than the original SAT-based ATPG algorithm.

Original languageEnglish
Pages (from-to)39-44
Number of pages6
JournalIPSJ Transactions on System LSI Design Methodology
Volume10
DOIs
Publication statusPublished - Feb 1 2017

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Automatic test pattern generation

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

An accelerating technique for SAT-based ATPG. / Matsunaga, Yusuke.

In: IPSJ Transactions on System LSI Design Methodology, Vol. 10, 01.02.2017, p. 39-44.

Research output: Contribution to journalArticle

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