TY - GEN

T1 - An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs

AU - Takata, Taiga

AU - Matsunaga, Yusuke

N1 - Copyright:
Copyright 2009 Elsevier B.V., All rights reserved.

PY - 2009

Y1 - 2009

N2 - Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to find good network, enumerating all cuts with large size consumes run-time very much. The number of cuts exponentially increases with the size of cuts, which causes long runtime. Furthermore, an inefficiency of bottom-up merging in existing algorithms makes the run-time much longer. This paper presents a novel cut enumeration. The proposed algorithm is efficient because it enumerates cuts without bottomup merging. Our algorithm has two modes; exhaustive enumeration and partial enumeration. Exhaustive enumeration enumerates all cuts. Partial enumeration enumerates partial cuts with a guarantee that a depth-minimum network can be constructed. The experimental results show that exhaustive enumeration runs about 3 times and 8 times faster than existing bottom-up algorithm [1] [2] for K = 8, 9, respectively. The quality of network are the same. Furthermore, partial enumeration runs about 6 times and 18 times faster than bottom-up algorithm for K = 8, 9, respectively. Area of network derived by the set of cuts enumerated by partial enumeration is only 4 % larger than that derived by exhaustive enumeration on average, and the depth is the same.

AB - Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to find good network, enumerating all cuts with large size consumes run-time very much. The number of cuts exponentially increases with the size of cuts, which causes long runtime. Furthermore, an inefficiency of bottom-up merging in existing algorithms makes the run-time much longer. This paper presents a novel cut enumeration. The proposed algorithm is efficient because it enumerates cuts without bottomup merging. Our algorithm has two modes; exhaustive enumeration and partial enumeration. Exhaustive enumeration enumerates all cuts. Partial enumeration enumerates partial cuts with a guarantee that a depth-minimum network can be constructed. The experimental results show that exhaustive enumeration runs about 3 times and 8 times faster than existing bottom-up algorithm [1] [2] for K = 8, 9, respectively. The quality of network are the same. Furthermore, partial enumeration runs about 6 times and 18 times faster than bottom-up algorithm for K = 8, 9, respectively. Area of network derived by the set of cuts enumerated by partial enumeration is only 4 % larger than that derived by exhaustive enumeration on average, and the depth is the same.

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U2 - 10.1145/1531542.1531622

DO - 10.1145/1531542.1531622

M3 - Conference contribution

AN - SCOPUS:70350607953

SN - 9781605585222

T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

SP - 351

EP - 356

BT - GLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI

T2 - 19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09

Y2 - 10 May 2009 through 12 May 2009

ER -