### Abstract

Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to find good network, enumerating all cuts with large size consumes run-time very much. The number of cuts exponentially increases with the size of cuts, which causes long runtime. Furthermore, an inefficiency of bottom-up merging in existing algorithms makes the run-time much longer. This paper presents a novel cut enumeration. The proposed algorithm is efficient because it enumerates cuts without bottomup merging. Our algorithm has two modes; exhaustive enumeration and partial enumeration. Exhaustive enumeration enumerates all cuts. Partial enumeration enumerates partial cuts with a guarantee that a depth-minimum network can be constructed. The experimental results show that exhaustive enumeration runs about 3 times and 8 times faster than existing bottom-up algorithm [1] [2] for K = 8, 9, respectively. The quality of network are the same. Furthermore, partial enumeration runs about 6 times and 18 times faster than bottom-up algorithm for K = 8, 9, respectively. Area of network derived by the set of cuts enumerated by partial enumeration is only 4 % larger than that derived by exhaustive enumeration on average, and the depth is the same.

Original language | English |
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Title of host publication | GLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI |

Pages | 351-356 |

Number of pages | 6 |

DOIs | |

Publication status | Published - 2009 |

Event | 19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 - Boston, MA, United States Duration: May 10 2009 → May 12 2009 |

### Other

Other | 19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 |
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Country | United States |

City | Boston, MA |

Period | 5/10/09 → 5/12/09 |

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### All Science Journal Classification (ASJC) codes

- Engineering(all)

### Cite this

*GLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI*(pp. 351-356) https://doi.org/10.1145/1531542.1531622