An estimation of encryption LSI testability against scan-based attack

Masayoshi Yoshimura, Yuma Ito, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recently, encryption LSIs are embedded in a variety of digital products for security and copyright protection. Most LSIs including encryption LSIs have scan paths for manufacturing tests. However, there is a risk that the secret information is leaked through scan paths. It is necessary to prevent side channel attacks to encryption LSIs. In this paper, we show all the factors for scan-based attacks to encryption LSIs. We propose a countermeasure that encryption LSIs are added to controllability and observability as possible under the condition that encryption LSI does not have all the factors which are necessary for scanbased attacks. We insert various structures of scan paths in DES chips and estimate testability and security of DES chips In addition, we propose the countermeasure against the scan-based attacks, and estimate the countermeasure from the viewpoints of testability and security. We show the trade-off between testability and security for various structures of scan path. The proposed countermeasure can achieve about 98% of high fault efficiency with preventing scan-based attack.

Original languageEnglish
Title of host publicationISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
Pages727-731
Number of pages5
DOIs
Publication statusPublished - Dec 1 2010
Event2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010 - Tokyo, Japan
Duration: Oct 26 2010Oct 29 2010

Publication series

NameISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies

Other

Other2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010
CountryJapan
CityTokyo
Period10/26/1010/29/10

Fingerprint

Cryptography
Observability
Controllability

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Information Systems

Cite this

Yoshimura, M., Ito, Y., & Yasuura, H. (2010). An estimation of encryption LSI testability against scan-based attack. In ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies (pp. 727-731). [5665083] (ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies). https://doi.org/10.1109/ISCIT.2010.5665083

An estimation of encryption LSI testability against scan-based attack. / Yoshimura, Masayoshi; Ito, Yuma; Yasuura, Hiroto.

ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies. 2010. p. 727-731 5665083 (ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoshimura, M, Ito, Y & Yasuura, H 2010, An estimation of encryption LSI testability against scan-based attack. in ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies., 5665083, ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies, pp. 727-731, 2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010, Tokyo, Japan, 10/26/10. https://doi.org/10.1109/ISCIT.2010.5665083
Yoshimura M, Ito Y, Yasuura H. An estimation of encryption LSI testability against scan-based attack. In ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies. 2010. p. 727-731. 5665083. (ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies). https://doi.org/10.1109/ISCIT.2010.5665083
Yoshimura, Masayoshi ; Ito, Yuma ; Yasuura, Hiroto. / An estimation of encryption LSI testability against scan-based attack. ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies. 2010. pp. 727-731 (ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies).
@inproceedings{4284cd62d1c146d09d92908381711497,
title = "An estimation of encryption LSI testability against scan-based attack",
abstract = "Recently, encryption LSIs are embedded in a variety of digital products for security and copyright protection. Most LSIs including encryption LSIs have scan paths for manufacturing tests. However, there is a risk that the secret information is leaked through scan paths. It is necessary to prevent side channel attacks to encryption LSIs. In this paper, we show all the factors for scan-based attacks to encryption LSIs. We propose a countermeasure that encryption LSIs are added to controllability and observability as possible under the condition that encryption LSI does not have all the factors which are necessary for scanbased attacks. We insert various structures of scan paths in DES chips and estimate testability and security of DES chips In addition, we propose the countermeasure against the scan-based attacks, and estimate the countermeasure from the viewpoints of testability and security. We show the trade-off between testability and security for various structures of scan path. The proposed countermeasure can achieve about 98{\%} of high fault efficiency with preventing scan-based attack.",
author = "Masayoshi Yoshimura and Yuma Ito and Hiroto Yasuura",
year = "2010",
month = "12",
day = "1",
doi = "10.1109/ISCIT.2010.5665083",
language = "English",
isbn = "9781424470105",
series = "ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies",
pages = "727--731",
booktitle = "ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies",

}

TY - GEN

T1 - An estimation of encryption LSI testability against scan-based attack

AU - Yoshimura, Masayoshi

AU - Ito, Yuma

AU - Yasuura, Hiroto

PY - 2010/12/1

Y1 - 2010/12/1

N2 - Recently, encryption LSIs are embedded in a variety of digital products for security and copyright protection. Most LSIs including encryption LSIs have scan paths for manufacturing tests. However, there is a risk that the secret information is leaked through scan paths. It is necessary to prevent side channel attacks to encryption LSIs. In this paper, we show all the factors for scan-based attacks to encryption LSIs. We propose a countermeasure that encryption LSIs are added to controllability and observability as possible under the condition that encryption LSI does not have all the factors which are necessary for scanbased attacks. We insert various structures of scan paths in DES chips and estimate testability and security of DES chips In addition, we propose the countermeasure against the scan-based attacks, and estimate the countermeasure from the viewpoints of testability and security. We show the trade-off between testability and security for various structures of scan path. The proposed countermeasure can achieve about 98% of high fault efficiency with preventing scan-based attack.

AB - Recently, encryption LSIs are embedded in a variety of digital products for security and copyright protection. Most LSIs including encryption LSIs have scan paths for manufacturing tests. However, there is a risk that the secret information is leaked through scan paths. It is necessary to prevent side channel attacks to encryption LSIs. In this paper, we show all the factors for scan-based attacks to encryption LSIs. We propose a countermeasure that encryption LSIs are added to controllability and observability as possible under the condition that encryption LSI does not have all the factors which are necessary for scanbased attacks. We insert various structures of scan paths in DES chips and estimate testability and security of DES chips In addition, we propose the countermeasure against the scan-based attacks, and estimate the countermeasure from the viewpoints of testability and security. We show the trade-off between testability and security for various structures of scan path. The proposed countermeasure can achieve about 98% of high fault efficiency with preventing scan-based attack.

UR - http://www.scopus.com/inward/record.url?scp=78651259295&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78651259295&partnerID=8YFLogxK

U2 - 10.1109/ISCIT.2010.5665083

DO - 10.1109/ISCIT.2010.5665083

M3 - Conference contribution

AN - SCOPUS:78651259295

SN - 9781424470105

T3 - ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies

SP - 727

EP - 731

BT - ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies

ER -