Abstract
Recently, encryption LSIs are embedded in a variety of digital products for security and copyright protection. Most LSIs including encryption LSIs have scan paths for manufacturing tests. However, there is a risk that the secret information is leaked through scan paths. It is necessary to prevent side channel attacks to encryption LSIs. In this paper, we show all the factors for scan-based attacks to encryption LSIs. We propose a countermeasure that encryption LSIs are added to controllability and observability as possible under the condition that encryption LSI does not have all the factors which are necessary for scanbased attacks. We insert various structures of scan paths in DES chips and estimate testability and security of DES chips In addition, we propose the countermeasure against the scan-based attacks, and estimate the countermeasure from the viewpoints of testability and security. We show the trade-off between testability and security for various structures of scan path. The proposed countermeasure can achieve about 98% of high fault efficiency with preventing scan-based attack.
| Original language | English |
|---|---|
| Title of host publication | ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies |
| Pages | 727-731 |
| Number of pages | 5 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010 - Tokyo, Japan Duration: Oct 26 2010 → Oct 29 2010 |
Other
| Other | 2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010 |
|---|---|
| Country | Japan |
| City | Tokyo |
| Period | 10/26/10 → 10/29/10 |
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All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Information Systems
Cite this
An estimation of encryption LSI testability against scan-based attack. / Yoshimura, Masayoshi; Ito, Yuma; Yasuura, Hiroto.
ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies. 2010. p. 727-731 5665083.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - An estimation of encryption LSI testability against scan-based attack
AU - Yoshimura, Masayoshi
AU - Ito, Yuma
AU - Yasuura, Hiroto
PY - 2010
Y1 - 2010
N2 - Recently, encryption LSIs are embedded in a variety of digital products for security and copyright protection. Most LSIs including encryption LSIs have scan paths for manufacturing tests. However, there is a risk that the secret information is leaked through scan paths. It is necessary to prevent side channel attacks to encryption LSIs. In this paper, we show all the factors for scan-based attacks to encryption LSIs. We propose a countermeasure that encryption LSIs are added to controllability and observability as possible under the condition that encryption LSI does not have all the factors which are necessary for scanbased attacks. We insert various structures of scan paths in DES chips and estimate testability and security of DES chips In addition, we propose the countermeasure against the scan-based attacks, and estimate the countermeasure from the viewpoints of testability and security. We show the trade-off between testability and security for various structures of scan path. The proposed countermeasure can achieve about 98% of high fault efficiency with preventing scan-based attack.
AB - Recently, encryption LSIs are embedded in a variety of digital products for security and copyright protection. Most LSIs including encryption LSIs have scan paths for manufacturing tests. However, there is a risk that the secret information is leaked through scan paths. It is necessary to prevent side channel attacks to encryption LSIs. In this paper, we show all the factors for scan-based attacks to encryption LSIs. We propose a countermeasure that encryption LSIs are added to controllability and observability as possible under the condition that encryption LSI does not have all the factors which are necessary for scanbased attacks. We insert various structures of scan paths in DES chips and estimate testability and security of DES chips In addition, we propose the countermeasure against the scan-based attacks, and estimate the countermeasure from the viewpoints of testability and security. We show the trade-off between testability and security for various structures of scan path. The proposed countermeasure can achieve about 98% of high fault efficiency with preventing scan-based attack.
UR - http://www.scopus.com/inward/record.url?scp=78651259295&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78651259295&partnerID=8YFLogxK
U2 - 10.1109/ISCIT.2010.5665083
DO - 10.1109/ISCIT.2010.5665083
M3 - Conference contribution
SN - 9781424470105
SP - 727
EP - 731
BT - ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
ER -