TY - GEN
T1 - Analysis and application of dual series resonances for low phase noise K-band VCO design in 0.18-μm CMOS technology
AU - Jahan, Nusrat
AU - Baichuan, Chen
AU - Barakat, Adel
AU - Pokharel, Ramesh K.
N1 - Funding Information:
This work is supported in part by a Grant-in-Aid for Scientific Research (C) (JP16K06301), and in part by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence and Keysight Corporations.
PY - 2019
Y1 - 2019
N2 - This work proposes a new theory to improve the phase noise of a Voltage-Controlled Oscillator (VCO) by introducing dual series resonances around the parallel resonance of an LC-tank circuit. The overall circuit has an improved susceptance slope parameters, which results in the improvement of quality (Q-) factor. Later, its effectiveness is demonstrated to design a low phase noise K-band VCO. The proposed characteristics are realized by a compact defected ground structure (DGS) resonator in a coplanar strip line (CPS) topology. The DGS is loaded by a capacitor, and this combination introduces the parallel resonance. The CPS signal line is implemented with high characteristic impedance to introduce a series inductance. Then, a gap in the CPS is introduced with a loading series capacitance forming a series resonance circuit with the CPS inductance. The overall combination of the series and parallel resonance circuits allowed the targeted two series resonances before and after the parallel resonance. The design is implemented in 0.18-μm CMOS technology, and the post-layout simulation shows that the VCO has a phase noise of -112.31 dBc/Hz @1 MHz offset of 22.07 GHz oscillation, which is 2.3 dB improvement compared to single series resonance VCO. The VCO consumes 4 mW power resulting in a figure of merit (FoM) of -193.2 dB.
AB - This work proposes a new theory to improve the phase noise of a Voltage-Controlled Oscillator (VCO) by introducing dual series resonances around the parallel resonance of an LC-tank circuit. The overall circuit has an improved susceptance slope parameters, which results in the improvement of quality (Q-) factor. Later, its effectiveness is demonstrated to design a low phase noise K-band VCO. The proposed characteristics are realized by a compact defected ground structure (DGS) resonator in a coplanar strip line (CPS) topology. The DGS is loaded by a capacitor, and this combination introduces the parallel resonance. The CPS signal line is implemented with high characteristic impedance to introduce a series inductance. Then, a gap in the CPS is introduced with a loading series capacitance forming a series resonance circuit with the CPS inductance. The overall combination of the series and parallel resonance circuits allowed the targeted two series resonances before and after the parallel resonance. The design is implemented in 0.18-μm CMOS technology, and the post-layout simulation shows that the VCO has a phase noise of -112.31 dBc/Hz @1 MHz offset of 22.07 GHz oscillation, which is 2.3 dB improvement compared to single series resonance VCO. The VCO consumes 4 mW power resulting in a figure of merit (FoM) of -193.2 dB.
UR - http://www.scopus.com/inward/record.url?scp=85066811379&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85066811379&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2019.8702264
DO - 10.1109/ISCAS.2019.8702264
M3 - Conference contribution
AN - SCOPUS:85066811379
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Y2 - 25 May 2019 through 28 May 2019
ER -