Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction

Takahiro Ota, Jun Imaoka, Masahito Shoyama, Hiroyuki Onishi, Shingo Nagaoka, Sadaharu Morishita

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a new design method to minimize the cause of parasitic oscillation in zero-current-switching (ZCS) DC-DC converter. The parasitic capacitance in switche is considered in circuit operation, a design of the ZCS DC-DC converter is optimized by proposed design method. With some prerequisites and assumptions, the waveform equations of the parasitic oscillations are analytically derived. The equations show the essential condition to suppress the parasitic oscillations and designing procedure of the auxiliary circuit. A 90 VDC/385 VDC, 300 W, operating 200 kHz prototype has been built and evaluated. The experimental results confirmed the validity and switch loss reduction effect of the proposed design method. The main switch loss has been measured approximately 37% smaller than conventional design method.

Original languageEnglish
Title of host publication2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509015467
DOIs
Publication statusPublished - Jan 1 2016
Event2nd IEEE Annual Southern Power Electronics Conference, SPEC 2016 - Auckland, New Zealand
Duration: Dec 5 2016Dec 8 2016

Publication series

Name2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016

Other

Other2nd IEEE Annual Southern Power Electronics Conference, SPEC 2016
CountryNew Zealand
CityAuckland
Period12/5/1612/8/16

All Science Journal Classification (ASJC) codes

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

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