Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction

Takahiro Ota, Jun Imaoka, Masahito Shoyama, Hiroyuki Onishi, Shingo Nagaoka, Sadaharu Morishita

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a new design method to minimize the cause of parasitic oscillation in zero-current-switching (ZCS) DC-DC converter. The parasitic capacitance in switche is considered in circuit operation, a design of the ZCS DC-DC converter is optimized by proposed design method. With some prerequisites and assumptions, the waveform equations of the parasitic oscillations are analytically derived. The equations show the essential condition to suppress the parasitic oscillations and designing procedure of the auxiliary circuit. A 90 VDC/385 VDC, 300 W, operating 200 kHz prototype has been built and evaluated. The experimental results confirmed the validity and switch loss reduction effect of the proposed design method. The main switch loss has been measured approximately 37% smaller than conventional design method.

Original languageEnglish
Title of host publication2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages114DUMMY
ISBN (Electronic)9781509015467
DOIs
Publication statusPublished - Jan 1 2016
Event2nd IEEE Annual Southern Power Electronics Conference, SPEC 2016 - Auckland, New Zealand
Duration: Dec 5 2016Dec 8 2016

Other

Other2nd IEEE Annual Southern Power Electronics Conference, SPEC 2016
CountryNew Zealand
CityAuckland
Period12/5/1612/8/16

Fingerprint

DC-DC converters
Capacitance
Switches
Networks (circuits)
Zero current switching

All Science Journal Classification (ASJC) codes

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

Cite this

Ota, T., Imaoka, J., Shoyama, M., Onishi, H., Nagaoka, S., & Morishita, S. (2016). Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction. In 2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016 (pp. 114DUMMY). [7846099] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SPEC.2016.7846099

Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction. / Ota, Takahiro; Imaoka, Jun; Shoyama, Masahito; Onishi, Hiroyuki; Nagaoka, Shingo; Morishita, Sadaharu.

2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 114DUMMY 7846099.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ota, T, Imaoka, J, Shoyama, M, Onishi, H, Nagaoka, S & Morishita, S 2016, Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction. in 2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016., 7846099, Institute of Electrical and Electronics Engineers Inc., pp. 114DUMMY, 2nd IEEE Annual Southern Power Electronics Conference, SPEC 2016, Auckland, New Zealand, 12/5/16. https://doi.org/10.1109/SPEC.2016.7846099
Ota T, Imaoka J, Shoyama M, Onishi H, Nagaoka S, Morishita S. Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction. In 2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 114DUMMY. 7846099 https://doi.org/10.1109/SPEC.2016.7846099
Ota, Takahiro ; Imaoka, Jun ; Shoyama, Masahito ; Onishi, Hiroyuki ; Nagaoka, Shingo ; Morishita, Sadaharu. / Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction. 2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 114DUMMY
@inproceedings{0878bab1fe30469381866474b013d2c8,
title = "Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction",
abstract = "This paper proposes a new design method to minimize the cause of parasitic oscillation in zero-current-switching (ZCS) DC-DC converter. The parasitic capacitance in switche is considered in circuit operation, a design of the ZCS DC-DC converter is optimized by proposed design method. With some prerequisites and assumptions, the waveform equations of the parasitic oscillations are analytically derived. The equations show the essential condition to suppress the parasitic oscillations and designing procedure of the auxiliary circuit. A 90 VDC/385 VDC, 300 W, operating 200 kHz prototype has been built and evaluated. The experimental results confirmed the validity and switch loss reduction effect of the proposed design method. The main switch loss has been measured approximately 37{\%} smaller than conventional design method.",
author = "Takahiro Ota and Jun Imaoka and Masahito Shoyama and Hiroyuki Onishi and Shingo Nagaoka and Sadaharu Morishita",
year = "2016",
month = "1",
day = "1",
doi = "10.1109/SPEC.2016.7846099",
language = "English",
pages = "114DUMMY",
booktitle = "2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction

AU - Ota, Takahiro

AU - Imaoka, Jun

AU - Shoyama, Masahito

AU - Onishi, Hiroyuki

AU - Nagaoka, Shingo

AU - Morishita, Sadaharu

PY - 2016/1/1

Y1 - 2016/1/1

N2 - This paper proposes a new design method to minimize the cause of parasitic oscillation in zero-current-switching (ZCS) DC-DC converter. The parasitic capacitance in switche is considered in circuit operation, a design of the ZCS DC-DC converter is optimized by proposed design method. With some prerequisites and assumptions, the waveform equations of the parasitic oscillations are analytically derived. The equations show the essential condition to suppress the parasitic oscillations and designing procedure of the auxiliary circuit. A 90 VDC/385 VDC, 300 W, operating 200 kHz prototype has been built and evaluated. The experimental results confirmed the validity and switch loss reduction effect of the proposed design method. The main switch loss has been measured approximately 37% smaller than conventional design method.

AB - This paper proposes a new design method to minimize the cause of parasitic oscillation in zero-current-switching (ZCS) DC-DC converter. The parasitic capacitance in switche is considered in circuit operation, a design of the ZCS DC-DC converter is optimized by proposed design method. With some prerequisites and assumptions, the waveform equations of the parasitic oscillations are analytically derived. The equations show the essential condition to suppress the parasitic oscillations and designing procedure of the auxiliary circuit. A 90 VDC/385 VDC, 300 W, operating 200 kHz prototype has been built and evaluated. The experimental results confirmed the validity and switch loss reduction effect of the proposed design method. The main switch loss has been measured approximately 37% smaller than conventional design method.

UR - http://www.scopus.com/inward/record.url?scp=85015284808&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85015284808&partnerID=8YFLogxK

U2 - 10.1109/SPEC.2016.7846099

DO - 10.1109/SPEC.2016.7846099

M3 - Conference contribution

SP - 114DUMMY

BT - 2016 IEEE 2nd Annual Southern Power Electronics Conference, SPEC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -