Analyzing the impact of data prefetching on chip multiprocessors

Naoto Fukumoto, Tomonobu Mihara, Inoue Koji, Kazuaki Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Data prefetching is a well known approach to compensating for poor memory performance, and has been employed in commercial processor chips. Although a number of prefetching techniques have so far been proposed, in many cases, they have assumed single-core architectures. In Chip Multiprocessor (or CMP) chips, there are some shared resources such as L2 caches, buses, and so on. Therefore, the effect of prefetching on CMP should be different from traditional single-core processors. In this paper, we analyze the effect of prefetching on CMP performance. This paper first classifies the impact of prefetches issued during program execution. Then, we discuss quantitatively the effect of prefetching to memory performance. The experimental results show that the negative effect of invalidation of prefetched cache blocks is very small. In addition, it is observed that the current prefetch algorithms do not exploit effectively the feature of CMPs, i.e. cache-to-cache on-chip data transfer.

Original languageEnglish
Title of host publication13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008
DOIs
Publication statusPublished - Nov 17 2008
Event13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008 - Hsinchu, Taiwan, Province of China
Duration: Aug 4 2008Aug 6 2008

Publication series

Name13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008

Other

Other13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008
CountryTaiwan, Province of China
CityHsinchu
Period8/4/088/6/08

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Fukumoto, N., Mihara, T., Koji, I., & Murakami, K. (2008). Analyzing the impact of data prefetching on chip multiprocessors. In 13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008 [4625454] (13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008). https://doi.org/10.1109/APCSAC.2008.4625454