TY - GEN
T1 - Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs
AU - Takata, Taiga
AU - Matsunaga, Yusuke
PY - 2008
Y1 - 2008
N2 - In this paper we present the post-processing algorithm, Cut Substitution, for technology mapping for LUT-based FPGAs to minimize the area under depth minimum constraint. The problem to generate a LUT's network whose area is minimum under depth minimum costraint seems to be as difficult as NP-Hard class problem. Cut Substitution is the process to generate a local optimum solution by eliminating redundant LUTs while the depth of network is maintained. The experiments shows that the proposed method derives the solutions whose area are 9% smaller than the solutions of a previous state-of-the-art, DAOmap on average.
AB - In this paper we present the post-processing algorithm, Cut Substitution, for technology mapping for LUT-based FPGAs to minimize the area under depth minimum constraint. The problem to generate a LUT's network whose area is minimum under depth minimum costraint seems to be as difficult as NP-Hard class problem. Cut Substitution is the process to generate a local optimum solution by eliminating redundant LUTs while the depth of network is maintained. The experiments shows that the proposed method derives the solutions whose area are 9% smaller than the solutions of a previous state-of-the-art, DAOmap on average.
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U2 - 10.1109/ASPDAC.2008.4483928
DO - 10.1109/ASPDAC.2008.4483928
M3 - Conference contribution
AN - SCOPUS:49549084115
SN - 9781424419227
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 144
EP - 147
BT - 2008 Asia and South Pacific Design Automation Conference, ASP-DAC
T2 - 2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Y2 - 21 March 2008 through 24 March 2008
ER -