Automatic generation of command level simulation model of a processor from RT level description

Hiroki Akaboshi, Hiroto Yasuura

Research output: Contribution to journalArticle

Abstract

In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations. A lower-level simulation model can simulate more accurately. There is little support for generating high-level simulation models in which a human designer is required. In this paper, an algorithm is proposed for high-level simulation model generation and experimental results are shown.

Original languageEnglish
Pages (from-to)35-45
Number of pages11
JournalElectronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume79
Issue number5
Publication statusPublished - May 1 1996

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Plant layout
Digital circuits
Microprocessor chips
Logic Synthesis

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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