### Abstract

In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits [1][2][3][4]. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with that of actual VLSI chip. To evaluate the accuracy of several kind of power dissipation model such as chip-level, block-level and gate-level etc., we examined as follows: (i) Measuring power consumption of actual microprocessors. (ii) Estimating power consumption with several kinds of power dissipation model. (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate.

Original language | English |
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Title of host publication | IEEE Symposium on Low Power Electronics |

Editors | Anon |

Publisher | IEEE |

Pages | 117-120 |

Number of pages | 4 |

Publication status | Published - 1996 |

Event | Proceedings of the 1996 International Symposium on Low Power Electronics and Design - Monterey, CA, USA Duration: Aug 12 1996 → Aug 14 1996 |

### Other

Other | Proceedings of the 1996 International Symposium on Low Power Electronics and Design |
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City | Monterey, CA, USA |

Period | 8/12/96 → 8/14/96 |

### Fingerprint

### All Science Journal Classification (ASJC) codes

- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials

### Cite this

*IEEE Symposium on Low Power Electronics*(pp. 117-120). IEEE.

**Basic experimentation on accuracy of power estimation for CMOS VLSI circuits.** / Ishihara, Tohru; Yasuura, Hiroto.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*IEEE Symposium on Low Power Electronics.*IEEE, pp. 117-120, Proceedings of the 1996 International Symposium on Low Power Electronics and Design, Monterey, CA, USA, 8/12/96.

}

TY - GEN

T1 - Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

AU - Ishihara, Tohru

AU - Yasuura, Hiroto

PY - 1996

Y1 - 1996

N2 - In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits [1][2][3][4]. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with that of actual VLSI chip. To evaluate the accuracy of several kind of power dissipation model such as chip-level, block-level and gate-level etc., we examined as follows: (i) Measuring power consumption of actual microprocessors. (ii) Estimating power consumption with several kinds of power dissipation model. (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate.

AB - In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits [1][2][3][4]. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with that of actual VLSI chip. To evaluate the accuracy of several kind of power dissipation model such as chip-level, block-level and gate-level etc., we examined as follows: (i) Measuring power consumption of actual microprocessors. (ii) Estimating power consumption with several kinds of power dissipation model. (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate.

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UR - http://www.scopus.com/inward/citedby.url?scp=0030385992&partnerID=8YFLogxK

M3 - Conference contribution

SP - 117

EP - 120

BT - IEEE Symposium on Low Power Electronics

A2 - Anon, null

PB - IEEE

ER -