Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

Tohru Ishihara, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits [1][2][3][4]. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with that of actual VLSI chip. To evaluate the accuracy of several kind of power dissipation model such as chip-level, block-level and gate-level etc., we examined as follows: (i) Measuring power consumption of actual microprocessors. (ii) Estimating power consumption with several kinds of power dissipation model. (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate.

Original languageEnglish
Title of host publicationInternational Symposium on Low Power Electronics and Design, Digest of Technical Papers
PublisherIEEE
Pages117-120
Number of pages4
Publication statusPublished - 1996
EventProceedings of the 1996 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
Duration: Aug 12 1996Aug 14 1996

Other

OtherProceedings of the 1996 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period8/12/968/14/96

Fingerprint

VLSI circuits
Energy dissipation
Electric power utilization
Microprocessor chips
Clocks
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Ishihara, T., & Yasuura, H. (1996). Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. In International Symposium on Low Power Electronics and Design, Digest of Technical Papers (pp. 117-120). IEEE.

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. / Ishihara, Tohru; Yasuura, Hiroto.

International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE, 1996. p. 117-120.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ishihara, T & Yasuura, H 1996, Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. in International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE, pp. 117-120, Proceedings of the 1996 International Symposium on Low Power Electronics and Design, Monterey, CA, USA, 8/12/96.
Ishihara T, Yasuura H. Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. In International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE. 1996. p. 117-120
Ishihara, Tohru ; Yasuura, Hiroto. / Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE, 1996. pp. 117-120
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