We propose a new architecture of functional memory type parallel procesor (FMPP) architectures called bit- parallel block-parallel (BPBP). FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel procesor architecture that has a memory-based simple two- dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of procesors. So far, a bit- serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP.
|Number of pages||8|
|Journal||IEICE Transactions on Electronics|
|Publication status||Published - Jul 1 1993|
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering