Bit-parallel block-parallel functional memory type parallel processor architecture

Kazutoshi Kobayashi, Keikichi Tamaru, Hirito Yasuura, Hidetoshi Onodera

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

We propose a new architecture of functional memory type parallel procesor (FMPP) architectures called bit- parallel block-parallel (BPBP). FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel procesor architecture that has a memory-based simple two- dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of procesors. So far, a bit- serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP.

Original languageEnglish
Pages (from-to)1151-1158
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE76-C
Issue number7
Publication statusPublished - Jul 1 1993
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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