Bit-parallel block-parallel functional memory type parallel processor architecture

Kazutoshi Kobayashi, Keikichi Tamaru, Hiroto Yasuura, Hidetoshi Onodera

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

We propose a new architecture of functional memory type parallel procesor (FMPP) architectures called bit- parallel block-parallel (BPBP). FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel procesor architecture that has a memory-based simple two- dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of procesors. So far, a bit- serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP.

Original languageEnglish
Pages (from-to)1151-1158
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE76-C
Issue number7
Publication statusPublished - Jul 1993
Externally publishedYes

Fingerprint

Data storage equipment
Parallel architectures
Associative storage

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Bit-parallel block-parallel functional memory type parallel processor architecture. / Kobayashi, Kazutoshi; Tamaru, Keikichi; Yasuura, Hiroto; Onodera, Hidetoshi.

In: IEICE Transactions on Electronics, Vol. E76-C, No. 7, 07.1993, p. 1151-1158.

Research output: Contribution to journalArticle

Kobayashi, Kazutoshi ; Tamaru, Keikichi ; Yasuura, Hiroto ; Onodera, Hidetoshi. / Bit-parallel block-parallel functional memory type parallel processor architecture. In: IEICE Transactions on Electronics. 1993 ; Vol. E76-C, No. 7. pp. 1151-1158.
@article{144606657c4c4a9fa40adbd6a3251dbe,
title = "Bit-parallel block-parallel functional memory type parallel processor architecture",
abstract = "We propose a new architecture of functional memory type parallel procesor (FMPP) architectures called bit- parallel block-parallel (BPBP). FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel procesor architecture that has a memory-based simple two- dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of procesors. So far, a bit- serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP.",
author = "Kazutoshi Kobayashi and Keikichi Tamaru and Hiroto Yasuura and Hidetoshi Onodera",
year = "1993",
month = "7",
language = "English",
volume = "E76-C",
pages = "1151--1158",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
number = "7",

}

TY - JOUR

T1 - Bit-parallel block-parallel functional memory type parallel processor architecture

AU - Kobayashi, Kazutoshi

AU - Tamaru, Keikichi

AU - Yasuura, Hiroto

AU - Onodera, Hidetoshi

PY - 1993/7

Y1 - 1993/7

N2 - We propose a new architecture of functional memory type parallel procesor (FMPP) architectures called bit- parallel block-parallel (BPBP). FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel procesor architecture that has a memory-based simple two- dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of procesors. So far, a bit- serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP.

AB - We propose a new architecture of functional memory type parallel procesor (FMPP) architectures called bit- parallel block-parallel (BPBP). FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel procesor architecture that has a memory-based simple two- dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of procesors. So far, a bit- serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP.

UR - http://www.scopus.com/inward/record.url?scp=0027634986&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027634986&partnerID=8YFLogxK

M3 - Article

VL - E76-C

SP - 1151

EP - 1158

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 7

ER -