Border-trap characterization for Ge gate stacks using deep-level transient spectroscopy

Hiroshi Nakashima, Wei Chen Wen, Keisuke Yamamoto, Dong Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A border trap (BT) evaluation method was established for SiO2/GeO2Ge gate stacks by using deep-level transient spectroscopy with a lock-in integrator. Ge metal-oxide-semiconductor capacitors (MOSCAPs) with SiCVGeCVGe gate stacks were fabricated by post-passivation thermal oxidation. The interface trap (IT) and BT signals were successfully separated based on their different dependences on the intensity of injection pulses. By using p-type MOSCAPs, BTs at the position of 0.4 nm from GeO2Ge interface were measured. The energy of these BTs was centralized at the position near to the valence band edge of Ge, and the density (Nbt) was in the range of 1017-1018 cm-3. For n-type MOSCAPs, BTs at the position range of 2.8-3.4 nm from the GeO2/Ge interface were measured. The energy of these BTs were distributed in a relatively wide range near to the conduction band edge of Ge, and the Nbt was approximately one order of magnitude higher than those for p-MOSCAPs. We also found that Al post metallization annealing can passivate both ITs and BTs near to the valence band edge of Ge but not those near to the conduction band edge.

Original languageEnglish
Title of host publicationSemiconductor Process Integration 11
EditorsJ. Murota, C. Claeys, H. Iwai, M. Tao, S. Deleonibus, A. Mai, K. Shiojima, Y. Cao
PublisherElectrochemical Society Inc.
Pages3-10
Number of pages8
Edition4
ISBN (Electronic)9781607685395
DOIs
Publication statusPublished - Jan 1 2019
Event11th Symposium on Semiconductor Process Integration - 236th ECS Meeting - Atlanta, United States
Duration: Oct 13 2019Oct 17 2019

Publication series

NameECS Transactions
Number4
Volume92
ISSN (Print)1938-6737
ISSN (Electronic)1938-5862

Conference

Conference11th Symposium on Semiconductor Process Integration - 236th ECS Meeting
CountryUnited States
CityAtlanta
Period10/13/1910/17/19

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Nakashima, H., Wen, W. C., Yamamoto, K., & Wang, D. (2019). Border-trap characterization for Ge gate stacks using deep-level transient spectroscopy. In J. Murota, C. Claeys, H. Iwai, M. Tao, S. Deleonibus, A. Mai, K. Shiojima, ... Y. Cao (Eds.), Semiconductor Process Integration 11 (4 ed., pp. 3-10). (ECS Transactions; Vol. 92, No. 4). Electrochemical Society Inc.. https://doi.org/10.1149/09204.0003ecsti