CAT (Critical-Area-Targeted): A new paradigm for reducing yield loss risk in at-speed scan testing

X. Wen, K. Enokimoto, K. Miyase, S. Kajihara, M. Aso, Hiroshi Furukawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

At-speed scan testing is essential in guaranteeing LSI chip quality in the deep-submicron era; however, chip/package damage, yield loss, and reliability degradation may occur in at-speed scan testing due to excessive test power, which can be several times higher than functional power. This problem is especially severe for low-power devices. In this paper, the background of the test power problem is reviewed, and the characteristics of two different types of test power (shift and capture) are highlighted. Then, a general strategy for test power reduction is described. After that, information on a novel CAT (critical-area-targeted) technique for tackling the more challenging problem of capture power reduction is provided. This unique and sophisticated technique can effectively reduces launch switching activity in a pinpoint manner by targeting at areas around long sensitized paths (called critical areas). Evaluation results on industrial circuits demonstrate the need for such CAT techniques.

Original languageEnglish
Title of host publicationChina Semiconductor Technology International Conference 2010, CSTIC 2010
Pages197-202
Number of pages6
Edition1
DOIs
Publication statusPublished - Dec 1 2010
EventChina Semiconductor Technology International Conference 2010, CSTIC 2010 - Shanghai, China
Duration: Mar 18 2010Mar 19 2010

Publication series

NameECS Transactions
Number1
Volume27
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherChina Semiconductor Technology International Conference 2010, CSTIC 2010
CountryChina
CityShanghai
Period3/18/103/19/10

Fingerprint

Testing
Degradation
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Wen, X., Enokimoto, K., Miyase, K., Kajihara, S., Aso, M., & Furukawa, H. (2010). CAT (Critical-Area-Targeted): A new paradigm for reducing yield loss risk in at-speed scan testing. In China Semiconductor Technology International Conference 2010, CSTIC 2010 (1 ed., pp. 197-202). (ECS Transactions; Vol. 27, No. 1). https://doi.org/10.1149/1.3360619

CAT (Critical-Area-Targeted) : A new paradigm for reducing yield loss risk in at-speed scan testing. / Wen, X.; Enokimoto, K.; Miyase, K.; Kajihara, S.; Aso, M.; Furukawa, Hiroshi.

China Semiconductor Technology International Conference 2010, CSTIC 2010. 1. ed. 2010. p. 197-202 (ECS Transactions; Vol. 27, No. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wen, X, Enokimoto, K, Miyase, K, Kajihara, S, Aso, M & Furukawa, H 2010, CAT (Critical-Area-Targeted): A new paradigm for reducing yield loss risk in at-speed scan testing. in China Semiconductor Technology International Conference 2010, CSTIC 2010. 1 edn, ECS Transactions, no. 1, vol. 27, pp. 197-202, China Semiconductor Technology International Conference 2010, CSTIC 2010, Shanghai, China, 3/18/10. https://doi.org/10.1149/1.3360619
Wen X, Enokimoto K, Miyase K, Kajihara S, Aso M, Furukawa H. CAT (Critical-Area-Targeted): A new paradigm for reducing yield loss risk in at-speed scan testing. In China Semiconductor Technology International Conference 2010, CSTIC 2010. 1 ed. 2010. p. 197-202. (ECS Transactions; 1). https://doi.org/10.1149/1.3360619
Wen, X. ; Enokimoto, K. ; Miyase, K. ; Kajihara, S. ; Aso, M. ; Furukawa, Hiroshi. / CAT (Critical-Area-Targeted) : A new paradigm for reducing yield loss risk in at-speed scan testing. China Semiconductor Technology International Conference 2010, CSTIC 2010. 1. ed. 2010. pp. 197-202 (ECS Transactions; 1).
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