Chip organization of bloch line memory

T. Suzuki, H. Asada, K. Matsuyama, E. Fujita, Y. Saegusa, K. Morikawa, K. Fujimoto, M. Shigenobu, K. Nakashi, B. Takamatsu, S. Konishi

Research output: Contribution to journalArticle

37 Citations (Scopus)

Abstract

A detailed and practical chip organization of Bloch line memory is proposed on the basis of preliminary experiments and computer simulations, The major line - minor loop organization is composed of two levels zigzag conductors to propagate bubbles (major line) and stripe domain walls surrounding grooved region where the epitaxial garnet layer is completely etched (minor loops), The garnet film thickness is chosen as one half of the usual bubble memory chip, which reduces the magneto-static attractive force between bubbles and between Bloch line pairs, and is preferable for Bloch line potential well generation to define bit position. New practical methods for VBL read-write operation are established by simulations and experiments.

Original languageEnglish
Pages (from-to)784-789
Number of pages6
JournalIEEE Transactions on Magnetics
Volume22
Issue number5
DOIs
Publication statusPublished - Sep 1986

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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