CMOS system LSI for processing IEEE 802.11B WLAN PHY signals through digital, analog baseband, and RF

T. Tsujimoto; H. Kanaya; K. Nakashi; K. Okamoto; K. Tarumi; T. Nakamura; H. Takatori; K. Hatano; T. Tsuchiya; K. Yoshida; Y. Kuroki; H. Yasuura

CMOS system LSI for processing IEEE 802.11B WLAN PHY signals through digital, analog baseband, and RF

T. Tsujimoto, H. Kanaya, K. Nakashi, K. Okamoto, K. Tarumi, T. Nakamura, H. Takatori, K. Hatano, T. Tsuchiya, K. Yoshida, Y. Kuroki, H. Yasuura

Research output: Contribution to conference › Paper › peer-review

Abstract

We study CMOS system LSI for radio communication implemented with low energy consumption (low power) and low cost as key device for mobile and ubiquitous computing. We designed the trial mixed-signal CMOS chip for 2.4GHz wireless LAN (IEEE 802.11b) in TSMC's 0.25um CMOS technology. As distinctive feature, coplanar waveguide (CPW) is used to realize the matching circuits placed between radio frequency (RF) amplifiers, at less cost than former inductor and capacitance (LC) circuit on chip. The trial chip operates the main functions of the 802.11b standard physical layer (PHY); carrier modulation by direct conversion, gain control, direct sequence spreading spectrum (DSSS), differential phase shift keying (DPSK) modulation, complementary code keying (CCK) modulation, framing the physical layer convergence procedure (PLCP) protocol data units (PPDUs), and, those reverse operations. This paper reports the structure of the trial chip containing RF circuits, base band analog circuits, and digital circuits on the very single chip.

Original language	English
Pages	17-20
Number of pages	4
Publication status	Published - 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan, Province of China Duration: Dec 6 2004 → Dec 9 2004

Other

Other	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan, Province of China
City	Tainan
Period	12/6/04 → 12/9/04

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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Tsujimoto, T., Kanaya, H., Nakashi, K., Okamoto, K., Tarumi, K., Nakamura, T., Takatori, H., Hatano, K., Tsuchiya, T., Yoshida, K., Kuroki, Y., & Yasuura, H. (2004). CMOS system LSI for processing IEEE 802.11B WLAN PHY signals through digital, analog baseband, and RF. 17-20. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, Province of China.

CMOS system LSI for processing IEEE 802.11B WLAN PHY signals through digital, analog baseband, and RF. / Tsujimoto, T.; Kanaya, H.; Nakashi, K. et al.

2004. 17-20 Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, Province of China.

Research output: Contribution to conference › Paper › peer-review

Tsujimoto, T, Kanaya, H, Nakashi, K, Okamoto, K, Tarumi, K, Nakamura, T, Takatori, H, Hatano, K, Tsuchiya, T, Yoshida, K, Kuroki, Y & Yasuura, H 2004, 'CMOS system LSI for processing IEEE 802.11B WLAN PHY signals through digital, analog baseband, and RF', Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, Province of China, 12/6/04 - 12/9/04 pp. 17-20.

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abstract = "We study CMOS system LSI for radio communication implemented with low energy consumption (low power) and low cost as key device for mobile and ubiquitous computing. We designed the trial mixed-signal CMOS chip for 2.4GHz wireless LAN (IEEE 802.11b) in TSMC's 0.25um CMOS technology. As distinctive feature, coplanar waveguide (CPW) is used to realize the matching circuits placed between radio frequency (RF) amplifiers, at less cost than former inductor and capacitance (LC) circuit on chip. The trial chip operates the main functions of the 802.11b standard physical layer (PHY); carrier modulation by direct conversion, gain control, direct sequence spreading spectrum (DSSS), differential phase shift keying (DPSK) modulation, complementary code keying (CCK) modulation, framing the physical layer convergence procedure (PLCP) protocol data units (PPDUs), and, those reverse operations. This paper reports the structure of the trial chip containing RF circuits, base band analog circuits, and digital circuits on the very single chip.",

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AU - Tsujimoto, T.

AU - Kanaya, H.

AU - Nakashi, K.

AU - Okamoto, K.

AU - Tarumi, K.

AU - Nakamura, T.

AU - Takatori, H.

AU - Hatano, K.

AU - Tsuchiya, T.

AU - Yoshida, K.

AU - Kuroki, Y.

AU - Yasuura, H.

PY - 2004

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N2 - We study CMOS system LSI for radio communication implemented with low energy consumption (low power) and low cost as key device for mobile and ubiquitous computing. We designed the trial mixed-signal CMOS chip for 2.4GHz wireless LAN (IEEE 802.11b) in TSMC's 0.25um CMOS technology. As distinctive feature, coplanar waveguide (CPW) is used to realize the matching circuits placed between radio frequency (RF) amplifiers, at less cost than former inductor and capacitance (LC) circuit on chip. The trial chip operates the main functions of the 802.11b standard physical layer (PHY); carrier modulation by direct conversion, gain control, direct sequence spreading spectrum (DSSS), differential phase shift keying (DPSK) modulation, complementary code keying (CCK) modulation, framing the physical layer convergence procedure (PLCP) protocol data units (PPDUs), and, those reverse operations. This paper reports the structure of the trial chip containing RF circuits, base band analog circuits, and digital circuits on the very single chip.

AB - We study CMOS system LSI for radio communication implemented with low energy consumption (low power) and low cost as key device for mobile and ubiquitous computing. We designed the trial mixed-signal CMOS chip for 2.4GHz wireless LAN (IEEE 802.11b) in TSMC's 0.25um CMOS technology. As distinctive feature, coplanar waveguide (CPW) is used to realize the matching circuits placed between radio frequency (RF) amplifiers, at less cost than former inductor and capacitance (LC) circuit on chip. The trial chip operates the main functions of the 802.11b standard physical layer (PHY); carrier modulation by direct conversion, gain control, direct sequence spreading spectrum (DSSS), differential phase shift keying (DPSK) modulation, complementary code keying (CCK) modulation, framing the physical layer convergence procedure (PLCP) protocol data units (PPDUs), and, those reverse operations. This paper reports the structure of the trial chip containing RF circuits, base band analog circuits, and digital circuits on the very single chip.

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CMOS system LSI for processing IEEE 802.11B WLAN PHY signals through digital, analog baseband, and RF

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All Science Journal Classification (ASJC) codes

UN SDGs

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