Code and data placement for embedded processors with scratchpad and cache memories

Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)

Abstract

This paper proposes a code placement problem, its ILP formulation, and a heuristic algorithm for reducing the total energy consumption of embedded processor systems including a CPU core, on-chip and off-chip memories. Our approach exploits a noncacheable memory region for an effective use of a cache memory and as a result, reduces the number of offchip accesses. Our algorithm simultaneously finds a code layout for a cacheable region, a scratchpad region, and the other non-cacheable region of the address space so as to minimize the total energy consumption of the processor system. Experiments using a commercial embedded processor and an off-chip SDRAM demonstrate that our algorithm reduces the energy consumption of the processor system by 23% without any performance degradation compared to the best result achieved by the conventional approach.

Original languageEnglish
Pages (from-to)211-224
Number of pages14
JournalJournal of Signal Processing Systems
Volume60
Issue number2
DOIs
Publication statusPublished - Aug 2010

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Theoretical Computer Science
  • Signal Processing
  • Information Systems
  • Modelling and Simulation
  • Hardware and Architecture

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