Code placement techniques for cache miss rate reduction

Hiroyuki Tomiyama, Hiroto Yasuura

Research output: Contribution to journalArticle

36 Citations (Scopus)

Abstract

In the design of embedded systems with cache memories, it is important to minimize the cache miss rates to reduce power consumption of the systems as well as improve the performance. In this article, we propose two code placement methods (a simplified method and a refined one) to reduce miss rates of instruction caches. We first define a simplified code placement problem without an attempt to minimize the code size. The problem is formulated as an integer linear programming (ILP) problem, by which an optimal placement can be found. Experimental results show that the simplified method reduces cache misses by an average of 30% (max. 77%). However, the code size obtained by the simplified method tends to be large, which inevitably leads to a larger memory size. In order to overcome this limitation, we further propose a refined code placement method in which the code size provided by the system designers must be satisfied. The effectiveness of the refined method is also demonstrated.

Original languageEnglish
Pages (from-to)410-429
Number of pages20
JournalACM Transactions on Design Automation of Electronic Systems
Volume2
Issue number4
DOIs
Publication statusPublished - Jan 1 1997

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Cache memory
Embedded systems
Linear programming
Electric power utilization
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Code placement techniques for cache miss rate reduction. / Tomiyama, Hiroyuki; Yasuura, Hiroto.

In: ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No. 4, 01.01.1997, p. 410-429.

Research output: Contribution to journalArticle

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