Comparison of parallel multipliers with neuron MOS and CMOS technologies

Kei Hirose, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

We intend to obtain a fast and high-density logic circuit combining neuron MOS transistors (neuMOS), that was developed in Tohoku university, into a binary logic circuit. In this paper, we focus on basic arithmetic functional circuits, a full-adder and a multiplier, and make a comparison of the area and delay of the neuMOS circuits with conventional CMOS logic circuits. The results of physical design and SPICE simulation show that the area of a neuMOS multiplier with full-adders decreases to about 65% of the area of CMOS, and the delay of a neuMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of CMOS.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
PublisherIEEE
Pages488-491
Number of pages4
Publication statusPublished - 1996
EventProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea
Duration: Nov 18 1996Nov 21 1996

Other

OtherProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems
CitySeoul, South Korea
Period11/18/9611/21/96

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Hirose, K., & Yasuura, H. (1996). Comparison of parallel multipliers with neuron MOS and CMOS technologies. In IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings (pp. 488-491). IEEE.