Abstract
We intend to obtain a fast and high-density logic circuit combining neuron MOS transistors (neuMOS), that was developed in Tohoku university, into a binary logic circuit. In this paper, we focus on basic arithmetic functional circuits, a full-adder and a multiplier, and make a comparison of the area and delay of the neuMOS circuits with conventional CMOS logic circuits. The results of physical design and SPICE simulation show that the area of a neuMOS multiplier with full-adders decreases to about 65% of the area of CMOS, and the delay of a neuMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of CMOS.
| Original language | English |
|---|---|
| Title of host publication | IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings |
| Publisher | IEEE |
| Pages | 488-491 |
| Number of pages | 4 |
| Publication status | Published - 1996 |
| Event | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea Duration: Nov 18 1996 → Nov 21 1996 |
Other
| Other | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems |
|---|---|
| City | Seoul, South Korea |
| Period | 11/18/96 → 11/21/96 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
Comparison of parallel multipliers with neuron MOS and CMOS technologies. / Hirose, Kei; Yasuura, Hiroto.
IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. IEEE, 1996. p. 488-491.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Comparison of parallel multipliers with neuron MOS and CMOS technologies
AU - Hirose, Kei
AU - Yasuura, Hiroto
PY - 1996
Y1 - 1996
N2 - We intend to obtain a fast and high-density logic circuit combining neuron MOS transistors (neuMOS), that was developed in Tohoku university, into a binary logic circuit. In this paper, we focus on basic arithmetic functional circuits, a full-adder and a multiplier, and make a comparison of the area and delay of the neuMOS circuits with conventional CMOS logic circuits. The results of physical design and SPICE simulation show that the area of a neuMOS multiplier with full-adders decreases to about 65% of the area of CMOS, and the delay of a neuMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of CMOS.
AB - We intend to obtain a fast and high-density logic circuit combining neuron MOS transistors (neuMOS), that was developed in Tohoku university, into a binary logic circuit. In this paper, we focus on basic arithmetic functional circuits, a full-adder and a multiplier, and make a comparison of the area and delay of the neuMOS circuits with conventional CMOS logic circuits. The results of physical design and SPICE simulation show that the area of a neuMOS multiplier with full-adders decreases to about 65% of the area of CMOS, and the delay of a neuMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of CMOS.
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UR - http://www.scopus.com/inward/citedby.url?scp=0030396433&partnerID=8YFLogxK
M3 - Conference contribution
SP - 488
EP - 491
BT - IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
PB - IEEE
ER -