Abstract
We have developed a compliant bump technology for 3D chip stacking with the same number of inter-chip connections as that in a VGA (video graphic array, 640 x 480). Using this technology together with a through-Si via (TSV) technology, we demonstrate a prototype of back-side illuminated CMOS image sensor, in which a very-thin rear-illuminated photodiode array is electrically connected to the CMOS readout circuit at a pixel level.
| Original language | English |
|---|---|
| Title of host publication | 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009 |
| Pages | 40-45 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - Oct 12 2009 |
| Event | 2009 59th Electronic Components and Technology Conference, ECTC 2009 - San Diego, CA, United States Duration: May 26 2009 → May 29 2009 |
Publication series
| Name | Proceedings - Electronic Components and Technology Conference |
|---|---|
| ISSN (Print) | 0569-5503 |
Other
| Other | 2009 59th Electronic Components and Technology Conference, ECTC 2009 |
|---|---|
| Country | United States |
| City | San Diego, CA |
| Period | 5/26/09 → 5/29/09 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Compliant bump technology for back-side illuminated CMOS image sensor. / Asano, Tanemasa; Watanabe, Naoya; Tsunoda, Isao; Kimiya, Yasuhiro; Fukunaga, Katsuaki; Handa, Minoru; Arao, Hiroki; Yamaji, Yasuhiro; Aoyagi, Masahiro; Higashimachi, Takao; Tanaka, Koichiro; Takao, Takayuki; Matsumura, Kimiharu; Ikeda, Akihiro; Kuroki, Yukinori; Tsurushima, Toshio.
2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009. 2009. p. 40-45 5073994 (Proceedings - Electronic Components and Technology Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Compliant bump technology for back-side illuminated CMOS image sensor
AU - Asano, Tanemasa
AU - Watanabe, Naoya
AU - Tsunoda, Isao
AU - Kimiya, Yasuhiro
AU - Fukunaga, Katsuaki
AU - Handa, Minoru
AU - Arao, Hiroki
AU - Yamaji, Yasuhiro
AU - Aoyagi, Masahiro
AU - Higashimachi, Takao
AU - Tanaka, Koichiro
AU - Takao, Takayuki
AU - Matsumura, Kimiharu
AU - Ikeda, Akihiro
AU - Kuroki, Yukinori
AU - Tsurushima, Toshio
PY - 2009/10/12
Y1 - 2009/10/12
N2 - We have developed a compliant bump technology for 3D chip stacking with the same number of inter-chip connections as that in a VGA (video graphic array, 640 x 480). Using this technology together with a through-Si via (TSV) technology, we demonstrate a prototype of back-side illuminated CMOS image sensor, in which a very-thin rear-illuminated photodiode array is electrically connected to the CMOS readout circuit at a pixel level.
AB - We have developed a compliant bump technology for 3D chip stacking with the same number of inter-chip connections as that in a VGA (video graphic array, 640 x 480). Using this technology together with a through-Si via (TSV) technology, we demonstrate a prototype of back-side illuminated CMOS image sensor, in which a very-thin rear-illuminated photodiode array is electrically connected to the CMOS readout circuit at a pixel level.
UR - http://www.scopus.com/inward/record.url?scp=70349668536&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70349668536&partnerID=8YFLogxK
U2 - 10.1109/ECTC.2009.5073994
DO - 10.1109/ECTC.2009.5073994
M3 - Conference contribution
AN - SCOPUS:70349668536
SN - 9781424444762
T3 - Proceedings - Electronic Components and Technology Conference
SP - 40
EP - 45
BT - 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009
ER -