Compliant bump technology for back-side illuminated CMOS image sensor

Tanemasa Asano; Naoya Watanabe; Isao Tsunoda; Yasuhiro Kimiya; Katsuaki Fukunaga; Minoru Handa; Hiroki Arao; Yasuhiro Yamaji; Masahiro Aoyagi; Takao Higashimachi; Koichiro Tanaka; Takayuki Takao; Kimiharu Matsumura; Akihiro Ikeda; Yukinori Kuroki; Toshio Tsurushima

doi:10.1109/ECTC.2009.5073994

Compliant bump technology for back-side illuminated CMOS image sensor

Tanemasa Asano, Naoya Watanabe, Isao Tsunoda, Yasuhiro Kimiya, Katsuaki Fukunaga, Minoru Handa, Hiroki Arao, Yasuhiro Yamaji, Masahiro Aoyagi, Takao Higashimachi, Koichiro Tanaka, Takayuki Takao, Kimiharu Matsumura, Akihiro Ikeda, Yukinori Kuroki, Toshio Tsurushima

Integrated Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

We have developed a compliant bump technology for 3D chip stacking with the same number of inter-chip connections as that in a VGA (video graphic array, 640 x 480). Using this technology together with a through-Si via (TSV) technology, we demonstrate a prototype of back-side illuminated CMOS image sensor, in which a very-thin rear-illuminated photodiode array is electrically connected to the CMOS readout circuit at a pixel level.

Original language	English
Title of host publication	2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009
Pages	40-45
Number of pages	6
DOIs	https://doi.org/10.1109/ECTC.2009.5073994
Publication status	Published - 2009
Event	2009 59th Electronic Components and Technology Conference, ECTC 2009 - San Diego, CA, United States Duration: May 26 2009 → May 29 2009

Publication series

Name	Proceedings - Electronic Components and Technology Conference
ISSN (Print)	0569-5503

Other

Other	2009 59th Electronic Components and Technology Conference, ECTC 2009
Country/Territory	United States
City	San Diego, CA
Period	5/26/09 → 5/29/09

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/ECTC.2009.5073994

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Asano, T., Watanabe, N., Tsunoda, I., Kimiya, Y., Fukunaga, K., Handa, M., Arao, H., Yamaji, Y., Aoyagi, M., Higashimachi, T., Tanaka, K., Takao, T., Matsumura, K., Ikeda, A., Kuroki, Y., & Tsurushima, T. (2009). Compliant bump technology for back-side illuminated CMOS image sensor. In 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009 (pp. 40-45). [5073994] (Proceedings - Electronic Components and Technology Conference). https://doi.org/10.1109/ECTC.2009.5073994

Compliant bump technology for back-side illuminated CMOS image sensor. / Asano, Tanemasa; Watanabe, Naoya; Tsunoda, Isao et al.

2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009. 2009. p. 40-45 5073994 (Proceedings - Electronic Components and Technology Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Asano, T, Watanabe, N, Tsunoda, I, Kimiya, Y, Fukunaga, K, Handa, M, Arao, H, Yamaji, Y, Aoyagi, M, Higashimachi, T, Tanaka, K, Takao, T, Matsumura, K, Ikeda, A, Kuroki, Y & Tsurushima, T 2009, Compliant bump technology for back-side illuminated CMOS image sensor. in 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009., 5073994, Proceedings - Electronic Components and Technology Conference, pp. 40-45, 2009 59th Electronic Components and Technology Conference, ECTC 2009, San Diego, CA, United States, 5/26/09. https://doi.org/10.1109/ECTC.2009.5073994

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AU - Asano, Tanemasa

AU - Watanabe, Naoya

AU - Tsunoda, Isao

AU - Kimiya, Yasuhiro

AU - Fukunaga, Katsuaki

AU - Handa, Minoru

AU - Arao, Hiroki

AU - Yamaji, Yasuhiro

AU - Aoyagi, Masahiro

AU - Higashimachi, Takao

AU - Tanaka, Koichiro

AU - Takao, Takayuki

AU - Matsumura, Kimiharu

AU - Ikeda, Akihiro

AU - Kuroki, Yukinori

AU - Tsurushima, Toshio

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AB - We have developed a compliant bump technology for 3D chip stacking with the same number of inter-chip connections as that in a VGA (video graphic array, 640 x 480). Using this technology together with a through-Si via (TSV) technology, we demonstrate a prototype of back-side illuminated CMOS image sensor, in which a very-thin rear-illuminated photodiode array is electrically connected to the CMOS readout circuit at a pixel level.

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Compliant bump technology for back-side illuminated CMOS image sensor

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