TY - GEN
T1 - Compliant bump technology for back-side illuminated CMOS image sensor
AU - Asano, Tanemasa
AU - Watanabe, Naoya
AU - Tsunoda, Isao
AU - Kimiya, Yasuhiro
AU - Fukunaga, Katsuaki
AU - Handa, Minoru
AU - Arao, Hiroki
AU - Yamaji, Yasuhiro
AU - Aoyagi, Masahiro
AU - Higashimachi, Takao
AU - Tanaka, Koichiro
AU - Takao, Takayuki
AU - Matsumura, Kimiharu
AU - Ikeda, Akihiro
AU - Kuroki, Yukinori
AU - Tsurushima, Toshio
N1 - Copyright:
Copyright 2009 Elsevier B.V., All rights reserved.
PY - 2009
Y1 - 2009
N2 - We have developed a compliant bump technology for 3D chip stacking with the same number of inter-chip connections as that in a VGA (video graphic array, 640 x 480). Using this technology together with a through-Si via (TSV) technology, we demonstrate a prototype of back-side illuminated CMOS image sensor, in which a very-thin rear-illuminated photodiode array is electrically connected to the CMOS readout circuit at a pixel level.
AB - We have developed a compliant bump technology for 3D chip stacking with the same number of inter-chip connections as that in a VGA (video graphic array, 640 x 480). Using this technology together with a through-Si via (TSV) technology, we demonstrate a prototype of back-side illuminated CMOS image sensor, in which a very-thin rear-illuminated photodiode array is electrically connected to the CMOS readout circuit at a pixel level.
UR - http://www.scopus.com/inward/record.url?scp=70349668536&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70349668536&partnerID=8YFLogxK
U2 - 10.1109/ECTC.2009.5073994
DO - 10.1109/ECTC.2009.5073994
M3 - Conference contribution
AN - SCOPUS:70349668536
SN - 9781424444762
T3 - Proceedings - Electronic Components and Technology Conference
SP - 40
EP - 45
BT - 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009
T2 - 2009 59th Electronic Components and Technology Conference, ECTC 2009
Y2 - 26 May 2009 through 29 May 2009
ER -