Coordinated power-performance optimization in manycores

Hiroshi Sasaki, Satoshi Imamura, Koji Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Citations (Scopus)

Abstract

Optimizing the performance in multiprogrammed environments, especially for workloads composed of multi-threaded programs is a desired feature of runtime management system in future manycore processors. At the same time, power capping capability is required in order to improve the reliability of microprocessor chips while reducing the costs of power supply and thermal budgeting. This paper presents a sophisticated runtime coordinated power-performance management system called C-3PO, which optimizes the performance of manycore processors under a power constraint by controlling two software knobs: thread packing, and dynamic voltage and frequency scaling (DVFS). The proposed solution distributes the power budget to each program by controlling the workload threads to be executed with appropriate number of cores and operating frequency. The power budget is distributed carefully in different forms (number of allocated cores or operating frequency) depending on the power-performance characteristics of the workload so that each program can effectively convert the power into performance. The proposed system is based on a heuristic algorithm which relies on runtime prediction of power and performance via hardware performance monitoring units. Empirical results on a 64-core platform show that C-3PO well outperforms traditional counterparts across various PARSEC workload mixes.

Original languageEnglish
Title of host publicationPACT 2013 - Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques
Pages51-61
Number of pages11
DOIs
Publication statusPublished - Nov 18 2013
Event22nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2013 - Edinburgh, United Kingdom
Duration: Sep 7 2013Sep 11 2013

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Other

Other22nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2013
CountryUnited Kingdom
CityEdinburgh
Period9/7/139/11/13

Fingerprint

Many-core
Performance Optimization
Workload
Knobs
Budget control
Heuristic algorithms
Microprocessor chips
Thread
Hardware
Monitoring
Performance Management
Performance Monitoring
Power Management
Costs
Microprocessor
Heuristic algorithm
Packing
Convert
Chip
Voltage

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

Cite this

Sasaki, H., Imamura, S., & Inoue, K. (2013). Coordinated power-performance optimization in manycores. In PACT 2013 - Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (pp. 51-61). [6618803] (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT). https://doi.org/10.1109/PACT.2013.6618803

Coordinated power-performance optimization in manycores. / Sasaki, Hiroshi; Imamura, Satoshi; Inoue, Koji.

PACT 2013 - Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques. 2013. p. 51-61 6618803 (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sasaki, H, Imamura, S & Inoue, K 2013, Coordinated power-performance optimization in manycores. in PACT 2013 - Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques., 6618803, Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, pp. 51-61, 22nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2013, Edinburgh, United Kingdom, 9/7/13. https://doi.org/10.1109/PACT.2013.6618803
Sasaki H, Imamura S, Inoue K. Coordinated power-performance optimization in manycores. In PACT 2013 - Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques. 2013. p. 51-61. 6618803. (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT). https://doi.org/10.1109/PACT.2013.6618803
Sasaki, Hiroshi ; Imamura, Satoshi ; Inoue, Koji. / Coordinated power-performance optimization in manycores. PACT 2013 - Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques. 2013. pp. 51-61 (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT).
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