CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.

Original languageEnglish
Title of host publicationProceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages166-172
Number of pages7
ISBN (Electronic)9781538620878
DOIs
Publication statusPublished - Apr 23 2018
Event5th International Symposium on Computing and Networking, CANDAR 2017 - Aomori, Japan
Duration: Nov 19 2017Nov 22 2017

Publication series

NameProceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017
Volume2018-January

Other

Other5th International Symposium on Computing and Networking, CANDAR 2017
CountryJapan
CityAomori
Period11/19/1711/22/17

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture

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    Tanimoto, T., Ono, T., & Inoue, K. (2018). CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors. In Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017 (pp. 166-172). (Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CANDAR.2017.60