CTX

A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing

Hiroshi Furukawa, X. Wen, K. Miyase, Y. Yamato, S. Kajihara, P. Girard, L. T. Wang, M. Tehranipoor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Abstract

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of don't care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.

Original languageEnglish
Title of host publicationProceedings of the 17th Asian Test Symposium, ATS 2008
Pages397-402
Number of pages6
DOIs
Publication statusPublished - Dec 1 2008
Event17th Asian Test Symposium, ATS 2008 - Sapporo, Japan
Duration: Nov 24 2008Nov 27 2008

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other17th Asian Test Symposium, ATS 2008
CountryJapan
CitySapporo
Period11/24/0811/27/08

Fingerprint

Clocks
Testing
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Furukawa, H., Wen, X., Miyase, K., Yamato, Y., Kajihara, S., Girard, P., ... Tehranipoor, M. (2008). CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. In Proceedings of the 17th Asian Test Symposium, ATS 2008 (pp. 397-402). [4711623] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2008.27

CTX : A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. / Furukawa, Hiroshi; Wen, X.; Miyase, K.; Yamato, Y.; Kajihara, S.; Girard, P.; Wang, L. T.; Tehranipoor, M.

Proceedings of the 17th Asian Test Symposium, ATS 2008. 2008. p. 397-402 4711623 (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Furukawa, H, Wen, X, Miyase, K, Yamato, Y, Kajihara, S, Girard, P, Wang, LT & Tehranipoor, M 2008, CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. in Proceedings of the 17th Asian Test Symposium, ATS 2008., 4711623, Proceedings of the Asian Test Symposium, pp. 397-402, 17th Asian Test Symposium, ATS 2008, Sapporo, Japan, 11/24/08. https://doi.org/10.1109/ATS.2008.27
Furukawa H, Wen X, Miyase K, Yamato Y, Kajihara S, Girard P et al. CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. In Proceedings of the 17th Asian Test Symposium, ATS 2008. 2008. p. 397-402. 4711623. (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2008.27
Furukawa, Hiroshi ; Wen, X. ; Miyase, K. ; Yamato, Y. ; Kajihara, S. ; Girard, P. ; Wang, L. T. ; Tehranipoor, M. / CTX : A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. Proceedings of the 17th Asian Test Symposium, ATS 2008. 2008. pp. 397-402 (Proceedings of the Asian Test Symposium).
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