Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic

Ikki Nagaoka; Masamitsu Tanaka; Kyosuke Sano; Taro Yamashita; Akira Fujimaki; Koji Inoue

doi:10.1109/ISEC46533.2019.8990905

Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic

Ikki Nagaoka, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Akira Fujimaki, Koji Inoue

Advanced Inormation and Communication Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm² Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).

Original language	English
Title of host publication	ISEC 2019 - International Superconductive Electronics Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728111964
DOIs	https://doi.org/10.1109/ISEC46533.2019.8990905
Publication status	Published - Jul 2019
Event	17th IEEE International Superconductive Electronics Conference, ISEC 2019 - Riverside, United States Duration: Jul 28 2019 → Aug 1 2019

Publication series

Name	ISEC 2019 - International Superconductive Electronics Conference

Conference

Conference	17th IEEE International Superconductive Electronics Conference, ISEC 2019
Country	United States
City	Riverside
Period	7/28/19 → 8/1/19

All Science Journal Classification (ASJC) codes

Fluid Flow and Transfer Processes
Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/ISEC46533.2019.8990905

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Nagaoka, I., Tanaka, M., Sano, K., Yamashita, T., Fujimaki, A., & Inoue, K. (2019). Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic. In ISEC 2019 - International Superconductive Electronics Conference [8990905] (ISEC 2019 - International Superconductive Electronics Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISEC46533.2019.8990905

Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic. / Nagaoka, Ikki; Tanaka, Masamitsu; Sano, Kyosuke; Yamashita, Taro; Fujimaki, Akira; Inoue, Koji.

ISEC 2019 - International Superconductive Electronics Conference. Institute of Electrical and Electronics Engineers Inc., 2019. 8990905 (ISEC 2019 - International Superconductive Electronics Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nagaoka, I, Tanaka, M, Sano, K, Yamashita, T, Fujimaki, A & Inoue, K 2019, Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic. in ISEC 2019 - International Superconductive Electronics Conference., 8990905, ISEC 2019 - International Superconductive Electronics Conference, Institute of Electrical and Electronics Engineers Inc., 17th IEEE International Superconductive Electronics Conference, ISEC 2019, Riverside, United States, 7/28/19. https://doi.org/10.1109/ISEC46533.2019.8990905

Nagaoka I, Tanaka M, Sano K, Yamashita T, Fujimaki A, Inoue K. Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic. In ISEC 2019 - International Superconductive Electronics Conference. Institute of Electrical and Electronics Engineers Inc. 2019. 8990905. (ISEC 2019 - International Superconductive Electronics Conference). https://doi.org/10.1109/ISEC46533.2019.8990905

Nagaoka, Ikki ; Tanaka, Masamitsu ; Sano, Kyosuke ; Yamashita, Taro ; Fujimaki, Akira ; Inoue, Koji. / Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic. ISEC 2019 - International Superconductive Electronics Conference. Institute of Electrical and Electronics Engineers Inc., 2019. (ISEC 2019 - International Superconductive Electronics Conference).

@inproceedings{0898b5db9aeb4c30874ba052160d9702,

title = "Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic",

abstract = "We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2 Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).",

author = "Ikki Nagaoka and Masamitsu Tanaka and Kyosuke Sano and Taro Yamashita and Akira Fujimaki and Koji Inoue",

year = "2019",

month = jul,

doi = "10.1109/ISEC46533.2019.8990905",

language = "English",

series = "ISEC 2019 - International Superconductive Electronics Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ISEC 2019 - International Superconductive Electronics Conference",

address = "United States",

note = "17th IEEE International Superconductive Electronics Conference, ISEC 2019 ; Conference date: 28-07-2019 Through 01-08-2019",

}

TY - GEN

T1 - Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic

AU - Nagaoka, Ikki

AU - Tanaka, Masamitsu

AU - Sano, Kyosuke

AU - Yamashita, Taro

AU - Fujimaki, Akira

AU - Inoue, Koji

PY - 2019/7

Y1 - 2019/7

N2 - We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2 Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).

AB - We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2 Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).

UR - http://www.scopus.com/inward/record.url?scp=85080112063&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85080112063&partnerID=8YFLogxK

U2 - 10.1109/ISEC46533.2019.8990905

DO - 10.1109/ISEC46533.2019.8990905

M3 - Conference contribution

T3 - ISEC 2019 - International Superconductive Electronics Conference

BT - ISEC 2019 - International Superconductive Electronics Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th IEEE International Superconductive Electronics Conference, ISEC 2019

Y2 - 28 July 2019 through 1 August 2019

ER -

Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic

Abstract

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All Science Journal Classification (ASJC) codes

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