TY - GEN
T1 - Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic
AU - Nagaoka, Ikki
AU - Tanaka, Masamitsu
AU - Sano, Kyosuke
AU - Yamashita, Taro
AU - Fujimaki, Akira
AU - Inoue, Koji
PY - 2019/7
Y1 - 2019/7
N2 - We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2 Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).
AB - We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2 Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).
UR - http://www.scopus.com/inward/record.url?scp=85080112063&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85080112063&partnerID=8YFLogxK
U2 - 10.1109/ISEC46533.2019.8990905
DO - 10.1109/ISEC46533.2019.8990905
M3 - Conference contribution
T3 - ISEC 2019 - International Superconductive Electronics Conference
BT - ISEC 2019 - International Superconductive Electronics Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th IEEE International Superconductive Electronics Conference, ISEC 2019
Y2 - 28 July 2019 through 1 August 2019
ER -