Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic

Ikki Nagaoka, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Akira Fujimaki, Koji Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2 Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).

Original languageEnglish
Title of host publicationISEC 2019 - International Superconductive Electronics Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728111964
DOIs
Publication statusPublished - Jul 2019
Event17th IEEE International Superconductive Electronics Conference, ISEC 2019 - Riverside, United States
Duration: Jul 28 2019Aug 1 2019

Publication series

NameISEC 2019 - International Superconductive Electronics Conference

Conference

Conference17th IEEE International Superconductive Electronics Conference, ISEC 2019
CountryUnited States
CityRiverside
Period7/28/198/1/19

All Science Journal Classification (ASJC) codes

  • Fluid Flow and Transfer Processes
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Fingerprint Dive into the research topics of 'Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic'. Together they form a unique fingerprint.

  • Cite this

    Nagaoka, I., Tanaka, M., Sano, K., Yamashita, T., Fujimaki, A., & Inoue, K. (2019). Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic. In ISEC 2019 - International Superconductive Electronics Conference [8990905] (ISEC 2019 - International Superconductive Electronics Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISEC46533.2019.8990905