Design and measurements of test element group wafer thinned to 10 μm for 3D system in package

Akihiro Ikeda, Tomonori Kuwata, Satoru Kajiwara, Tsuyoshi Fujimura, Hisao Kuriyaki, Reiji Hattori, Hiroshi Ogi, Kiyoshi Hamaguchi, Yukinori Kuroki

Research output: Contribution to conferencePaper

13 Citations (Scopus)

Abstract

We designed and measured test element group wafers thinned to 10μm for 3D system in package. The n-well - p-Si diodes in 10 μm thick wafer showed increasing of the reverse saturation current in comparison to the currents in 20μm, 30 μm or 640 μm thick wafer. While the pMOSFETs and nMOSFETs in 10μm thick wafer showed no degradation of mobility, sub-threshold swing and threshold voltage. Defects might be induced by mechanical stress during wafer back grinding process near wafer back side, within a few micron-meters from the wafer back surface.

Original languageEnglish
Pages161-164
Number of pages4
Publication statusPublished - Jul 12 2004
EventProceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004) - Awaji, Japan
Duration: Mar 22 2004Mar 25 2004

Other

OtherProceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004)
CountryJapan
CityAwaji
Period3/22/043/25/04

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Ikeda, A., Kuwata, T., Kajiwara, S., Fujimura, T., Kuriyaki, H., Hattori, R., Ogi, H., Hamaguchi, K., & Kuroki, Y. (2004). Design and measurements of test element group wafer thinned to 10 μm for 3D system in package. 161-164. Paper presented at Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004), Awaji, Japan.