Design and measurements of test element group wafer thinned to 10 μm for 3D system in package

Akihiro Ikeda; Tomonori Kuwata; Satoru Kajiwara; Tsuyoshi Fujimura; Hisao Kuriyaki; Reiji Hattori; Hiroshi Ogi; Kiyoshi Hamaguchi; Yukinori Kuroki

Design and measurements of test element group wafer thinned to 10 μm for 3D system in package

Akihiro Ikeda, Tomonori Kuwata, Satoru Kajiwara, Tsuyoshi Fujimura, Hisao Kuriyaki, Reiji Hattori, Hiroshi Ogi, Kiyoshi Hamaguchi, Yukinori Kuroki

Research output: Contribution to conference › Paper › peer-review

14 Citations (Scopus)

Abstract

We designed and measured test element group wafers thinned to 10μm for 3D system in package. The n-well - p-Si diodes in 10 μm thick wafer showed increasing of the reverse saturation current in comparison to the currents in 20μm, 30 μm or 640 μm thick wafer. While the pMOSFETs and nMOSFETs in 10μm thick wafer showed no degradation of mobility, sub-threshold swing and threshold voltage. Defects might be induced by mechanical stress during wafer back grinding process near wafer back side, within a few micron-meters from the wafer back surface.

Original language	English
Pages	161-164
Number of pages	4
Publication status	Published - Jul 12 2004
Event	Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004) - Awaji, Japan Duration: Mar 22 2004 → Mar 25 2004

Other

Other	Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004)
Country/Territory	Japan
City	Awaji
Period	3/22/04 → 3/25/04

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

Ikeda, A, Kuwata, T, Kajiwara, S, Fujimura, T, Kuriyaki, H, Hattori, R, Ogi, H, Hamaguchi, K & Kuroki, Y 2004, 'Design and measurements of test element group wafer thinned to 10 μm for 3D system in package', Paper presented at Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004), Awaji, Japan, 3/22/04 - 3/25/04 pp. 161-164.

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title = "Design and measurements of test element group wafer thinned to 10 μm for 3D system in package",

abstract = "We designed and measured test element group wafers thinned to 10μm for 3D system in package. The n-well - p-Si diodes in 10 μm thick wafer showed increasing of the reverse saturation current in comparison to the currents in 20μm, 30 μm or 640 μm thick wafer. While the pMOSFETs and nMOSFETs in 10μm thick wafer showed no degradation of mobility, sub-threshold swing and threshold voltage. Defects might be induced by mechanical stress during wafer back grinding process near wafer back side, within a few micron-meters from the wafer back surface.",

author = "Akihiro Ikeda and Tomonori Kuwata and Satoru Kajiwara and Tsuyoshi Fujimura and Hisao Kuriyaki and Reiji Hattori and Hiroshi Ogi and Kiyoshi Hamaguchi and Yukinori Kuroki",

year = "2004",

month = jul,

day = "12",

language = "English",

pages = "161--164",

note = "Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004) ; Conference date: 22-03-2004 Through 25-03-2004",

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TY - CONF

T1 - Design and measurements of test element group wafer thinned to 10 μm for 3D system in package

AU - Ikeda, Akihiro

AU - Kuwata, Tomonori

AU - Kajiwara, Satoru

AU - Fujimura, Tsuyoshi

AU - Kuriyaki, Hisao

AU - Hattori, Reiji

AU - Ogi, Hiroshi

AU - Hamaguchi, Kiyoshi

AU - Kuroki, Yukinori

PY - 2004/7/12

Y1 - 2004/7/12

N2 - We designed and measured test element group wafers thinned to 10μm for 3D system in package. The n-well - p-Si diodes in 10 μm thick wafer showed increasing of the reverse saturation current in comparison to the currents in 20μm, 30 μm or 640 μm thick wafer. While the pMOSFETs and nMOSFETs in 10μm thick wafer showed no degradation of mobility, sub-threshold swing and threshold voltage. Defects might be induced by mechanical stress during wafer back grinding process near wafer back side, within a few micron-meters from the wafer back surface.

AB - We designed and measured test element group wafers thinned to 10μm for 3D system in package. The n-well - p-Si diodes in 10 μm thick wafer showed increasing of the reverse saturation current in comparison to the currents in 20μm, 30 μm or 640 μm thick wafer. While the pMOSFETs and nMOSFETs in 10μm thick wafer showed no degradation of mobility, sub-threshold swing and threshold voltage. Defects might be induced by mechanical stress during wafer back grinding process near wafer back side, within a few micron-meters from the wafer back surface.

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M3 - Paper

AN - SCOPUS:3042611449

SP - 161

EP - 164

T2 - Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004)

Y2 - 22 March 2004 through 25 March 2004

ER -

Design and measurements of test element group wafer thinned to 10 μm for 3D system in package

Abstract

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All Science Journal Classification (ASJC) codes

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