Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class semi-super junction MOSFET

Syotaro Ono, Wataru Saito, Masakatsu Takashita, Shoichiro Kurushima, Ken'ichi Tokano, Masakazu Yamaguchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

We report the experimental results detailed about the n-buffer layer (n-BAL: n-Bottom Assist Layer) of 600V-class Semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance (RonA) and the breakdown voltage (V B), the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio TBAL-ratio and the doping concentration NBAL were varied in this work. As a result, the VB=750V, the RonA=24.6mΩcm2, the maximum avalanche current density JAP=292A/cm2 (I AP=7.6A, EAS=1.25J/cm2), and softness factor=0.277 were obtained with the structure of TBAL-ratio=27% and NBAL=1.0×1015 cm-3. The demonstration results showed that NPT (Non Punch Through)-type design (with high T BAL-ratio and high NBAL) realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (Punch Through)-type design.

Original languageEnglish
Title of host publicationProceedings of 19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07
Pages25-28
Number of pages4
DOIs
Publication statusPublished - Dec 1 2007
Externally publishedYes
Event19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07 - Jeju Island, Korea, Republic of
Duration: May 27 2007May 31 2007

Publication series

NameProceedings of the International Symposium on Power Semiconductor Devices and ICs
ISSN (Print)1063-6854

Other

Other19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07
CountryKorea, Republic of
CityJeju Island
Period5/27/075/31/07

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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