Design of 1.1 GHz highly linear digitally-controlled ring oscillator with wide tuning range

A. Tomar; Ramesh Pokharel; O. Nizhnik; Haruichi Kanaya; K. Yoshida

doi:10.1109/RFIT.2007.4443926

Design of 1.1 GHz highly linear digitally-controlled ring oscillator with wide tuning range

A. Tomar, Ramesh Pokharel, O. Nizhnik, Haruichi Kanaya, K. Yoshida

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Citations (Scopus)

Abstract

This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.35um CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from 333 MHz to 1472 MHz with very good linearity. The output voltage swing is constant and above 3volt (>90% of the supply voltage i.e. 3.3V). The presented circuit shows the fast response to the output frequency transition and this takes less than one clock period and without showing any ringing or damping during frequency transition. The proposed DCO has simulated phase noise of -106dBc/Hz @1Mhz and 63.4 mw power consumption at 1.1 GHz central frequency.

Original language	English
Title of host publication	RFIT 2007 - IEEE International Workshop on Radio-Frequency Integration Technology
Pages	82-85
Number of pages	4
DOIs	https://doi.org/10.1109/RFIT.2007.4443926
Publication status	Published - Dec 1 2007
Event	IEEE International Workshop on Radio-Frequency Integration Technology, RFIT 2007 - Singapore, Singapore Duration: Dec 9 2007 → Dec 11 2007

Other

Other	IEEE International Workshop on Radio-Frequency Integration Technology, RFIT 2007
Country	Singapore
City	Singapore
Period	12/9/07 → 12/11/07

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Electrical and Electronic Engineering
Communication

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10.1109/RFIT.2007.4443926

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Tomar, A, Pokharel, R, Nizhnik, O, Kanaya, H & Yoshida, K 2007, Design of 1.1 GHz highly linear digitally-controlled ring oscillator with wide tuning range. in RFIT 2007 - IEEE International Workshop on Radio-Frequency Integration Technology., 4443926, pp. 82-85, IEEE International Workshop on Radio-Frequency Integration Technology, RFIT 2007, Singapore, Singapore, 12/9/07. https://doi.org/10.1109/RFIT.2007.4443926

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abstract = "This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.35um CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from 333 MHz to 1472 MHz with very good linearity. The output voltage swing is constant and above 3volt (>90% of the supply voltage i.e. 3.3V). The presented circuit shows the fast response to the output frequency transition and this takes less than one clock period and without showing any ringing or damping during frequency transition. The proposed DCO has simulated phase noise of -106dBc/Hz @1Mhz and 63.4 mw power consumption at 1.1 GHz central frequency.",

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AU - Tomar, A.

AU - Pokharel, Ramesh

AU - Nizhnik, O.

AU - Kanaya, Haruichi

AU - Yoshida, K.

PY - 2007/12/1

Y1 - 2007/12/1

N2 - This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.35um CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from 333 MHz to 1472 MHz with very good linearity. The output voltage swing is constant and above 3volt (>90% of the supply voltage i.e. 3.3V). The presented circuit shows the fast response to the output frequency transition and this takes less than one clock period and without showing any ringing or damping during frequency transition. The proposed DCO has simulated phase noise of -106dBc/Hz @1Mhz and 63.4 mw power consumption at 1.1 GHz central frequency.

AB - This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.35um CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from 333 MHz to 1472 MHz with very good linearity. The output voltage swing is constant and above 3volt (>90% of the supply voltage i.e. 3.3V). The presented circuit shows the fast response to the output frequency transition and this takes less than one clock period and without showing any ringing or damping during frequency transition. The proposed DCO has simulated phase noise of -106dBc/Hz @1Mhz and 63.4 mw power consumption at 1.1 GHz central frequency.

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BT - RFIT 2007 - IEEE International Workshop on Radio-Frequency Integration Technology

T2 - IEEE International Workshop on Radio-Frequency Integration Technology, RFIT 2007

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